[flashrom] Board enable for EPoX EP-8RDA3+ lspci fix
Luc Verhaegen
libv at skynet.be
Mon Oct 5 13:45:09 CEST 2009
On Mon, Oct 05, 2009 at 03:40:16AM +0200, Luc Verhaegen wrote:
>
> Patch is slightly off.
>
> Fixed up version attached.
>
> Luc Verhaegen.
Since we will soon have 3 very similar board enables for nvidia MCPs
i have altered the patch.
Luc Verhaegen.
-------------- next part --------------
Board enable for EPoX EP-8RDA3+.
SocketA + nForce2.
Motherboard includes a second ethernet controller and an Agere
firewire controller with valid subsystem ids, so these are used for
matching the board.
This patch unifies the setting of what i think are gpio lines on
nvidia MCPs. Now used by both board_ga_k8n_sli and the now
introduced board_epox_ep_8rda3plus.
Signed-off-by: Luc Verhaegen <libv at skynet.be>
Index: board_enable.c
===================================================================
--- board_enable.c (revision 743)
+++ board_enable.c (working copy)
@@ -400,13 +400,30 @@
}
/**
+ * No docs, so we are just guessing that these might be individual gpio lines.
+ */
+static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset)
+{
+ uint16_t base;
+ uint8_t tmp;
+
+ base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
+
+ base += 0xC0;
+
+ /* if anyone knows more about nvidia mcps, feel free to explain this */
+ tmp = INB(base + offset);
+ tmp &= ~0x0F;
+ tmp |= 0x05;
+ OUTB(tmp, base + offset);
+}
+
+/**
* Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
*/
static int board_ga_k8n_sli(const char *name)
{
struct pci_dev *dev;
- uint32_t base;
- uint8_t tmp;
dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */
if (!dev) {
@@ -414,16 +431,30 @@
return -1;
}
- base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
+ nvidia_mcp_gpio_raise(dev, 0x21);
- /* if anyone knows more about nvidia lpcs, feel free to explain this */
- tmp = INB(base + 0xE1);
- tmp |= 0x05;
- OUTB(tmp, base + 0xE1);
+ return 0;
+}
+/**
+ * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400.
+ */
+static int board_epox_ep_8rda3plus(const char *name)
+{
+ struct pci_dev *dev;
+
+ dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */
+ if (!dev) {
+ fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n");
+ return -1;
+ }
+
+ nvidia_mcp_gpio_raise(dev, 0x31);
+
return 0;
}
+
static int board_hp_dl145_g3_enable(const char *name)
{
/* Set GPIO lines in the Broadcom HT-1000 southbridge. */
@@ -1006,6 +1037,7 @@
{0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise},
{0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},
{0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2},
+ {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus},
{0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
{0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash},
{0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable},
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