[flashrom] bad flash ?

Luc Verhaegen libv at skynet.be
Fri Jul 17 22:58:29 CEST 2009


On Fri, Jul 17, 2009 at 07:33:15PM +0200, Benjamin BELLEC wrote:
> Hello,
> I have tried to flash the BIOS of my motherboard. It's a Gigabyte 
> G33M-DS2R (ICH9R + SST SST25VF080B" (1024 KB)).
> 
> [root at scarabee benjamin]# flashrom --version
> flashrom v0.9.0
> 
> (on Fedora 11 x86_64)
> 
> Here is the log of the flash (my motherboard was previously in version F7) :
> 
> flashrom --write ./G33MDS2R.F8
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel ICH9R", enabling flash write... OK.
> Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
> ===
> This flash part has status UNTESTED for operations: READ ERASE WRITE
> Please email a report to flashrom at coreboot.org if any of the above 
> operations
> work correctly for you with this flash part. Please include the full output
> from the program, including chipset found. Thank you for your help!
> ===
> Flash image seems to be a legacy BIOS. Disabling checks.
> Programming page:
> 
> [root at scarabee motherboard_bios_ga-g33m-ds2r_f8]#
> 
> 
> and I check the BIOS :
> 
> [root at scarabee motherboard_bios_ga-g33m-ds2r_f8]# flashrom --verify 
> ./G33MDS2R.F8
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel ICH9R", enabling flash write... OK.
> Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
> ===
> This flash part has status UNTESTED for operations: READ ERASE WRITE
> Please email a report to flashrom at coreboot.org if any of the above 
> operations
> work correctly for you with this flash part. Please include the full output
> from the program, including chipset found. Thank you for your help!
> ===
> Flash image seems to be a legacy BIOS. Disabling checks.
> Verifying flash... FAILED at 0x00000000!  Expected=0x00, Read=0x01
> [root at scarabee motherboard_bios_ga-g33m-ds2r_f8]#
> 
> 
> and when I try to erase it :
> 
> [root at scarabee benjamin]# flashrom --erase
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel ICH9R", enabling flash write... OK.
> Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
> ===
> This flash part has status UNTESTED for operations: READ ERASE WRITE
> Please email a report to flashrom at coreboot.org if any of the above 
> operations
> work correctly for you with this flash part. Please include the full output
> from the program, including chipset found. Thank you for your help!
> ===
> Erasing flash chip... FAILED!
> ERROR at 0x00000000: Expected=0xff, Read=0x01
> [root at scarabee benjamin]#
> 
> I can post the entire log (--write --verbose) if you want.
> 
> What can I do, is my BIOS really write or not ? Can I reboot ?
> 
> Thanks for your time.
> 
> Benjamin (from France)

The board enable is plainly the chipset enable, so that's not it.

Carldani? Uwe? Any ideas here?

Luc Verhaegen.




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