[flashrom] Asus A7V8X needs a board enable.

[Luc Verhaegen]

On Sun, Jul 05, 2009 at 03:05:59PM +0200, Luc Verhaegen wrote:
> 
> Board enable requires two things:
> 
>     io(0x370) &= ~0x02;
>     io(PM_IO_Base + 0x2C) |= 0x01;
> 
> The second scarily translates to: "Enable SMI generation".
> 
> The first is (according to carldani) most likely an io range for the 
> super io. The superio is probably an it8712, but we do not know for 
> sure, but there is a good chance that this is about dropping a gpio
> line. We might then get lucky and might not need SMI at all.

Ok, here it is... A first stab at a board enable... Not the way it 
should be, but we have little other option.

Glenn, apply on top of a clean flashrom tree.

Luc Verhaegen.
-------------- next part --------------
Add potential board enable for Asus A7V8X.

We sadly do not have enough information on the superio of this board,
and are unable to properly dump registers from it. Current theory is
that 0x370 is the gpio simple io base, and that we are dropping gpio1.

Signed-off-by: Luc Verhaegen <libv at skynet.be>

Index: board_enable.c
===================================================================
--- board_enable.c	(revision 642)
+++ board_enable.c	(working copy)
@@ -832,6 +832,24 @@
 }
 
 /**
+ * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
+ */
+static int board_asus_a7v8x(const char *name)
+{
+	uint8_t tmp;
+
+	/* We assume that this is simple IO access of gpio1 on the it8703F.
+	 * But we are currently unable to dump the registers of the it878703F
+	 * correctly to verify this and no datasheet is available for this one.
+	 */
+	tmp = INB(0x370);
+	tmp &= ~0x02;
+	OUTB(tmp, 0x370);
+
+	return 0;
+}
+
+/**
  * We use 2 sets of IDs here, you're free to choose which is which. This
  * is to provide a very high degree of certainty when matching a board on
  * the basis of subsystem/card IDs. As not every vendor handles
@@ -860,6 +878,7 @@
 	{0x1106, 0x3177, 0x17F2, 0x3177,  0x1106, 0x3148, 0x17F2, 0x3148, NULL,         NULL,          "Albatron",    "PM266A*",            board_epox_ep_8k5a2},
 	{0x1022, 0x2090,      0,      0,  0x1022, 0x2080,      0,      0, "artecgroup", "dbe61",       "Artec Group", "DBE61",              board_artecgroup_dbe6x},
 	{0x1022, 0x2090,      0,      0,  0x1022, 0x2080,      0,      0, "artecgroup", "dbe62",       "Artec Group", "DBE62",              board_artecgroup_dbe6x},
+	{0x1106, 0x3189, 0x1043, 0x807F,  0x1106, 0x3177, 0x1043, 0x808C, NULL,         NULL,          "ASUS",        "A7V8X",              board_asus_a7v8x},
 	{0x1106, 0x3177, 0x1043, 0x80A1,  0x1106, 0x3205, 0x1043, 0x8118, NULL,         NULL,          "ASUS",        "A7V8X-MX SE",        board_asus_a7v8x_mx},
 	{0x8086, 0x1a30, 0x1043, 0x8070,  0x8086, 0x244b, 0x1043, 0x8028, NULL,         NULL,          "ASUS",        "P4B266",             ich2_gpio22_raise},
 	{0x10B9, 0x1541,      0,      0,  0x10B9, 0x1533,      0,      0, "asus",       "p5a",         "ASUS",        "P5A",                board_asus_p5a},