<html>
  <head>
    <meta content="text/html; charset=utf-8" http-equiv="Content-Type">
  </head>
  <body bgcolor="#FFFFFF" text="#000000">
    <div class="moz-cite-prefix">Thank you all for your support,<br>
      My x201 is a Nehalem architecture, not IVB (Ivy Bidge I suppose)<br>
      <br>
      On 11/23/2016 02:40 AM, Charlotte Plusplus wrote:<br>
    </div>
    <blockquote
cite="mid:CA+=e9eM2Z+azRLC72hwbhQN765X2U_m6j3RYKcN8wHO2bh+_LQ@mail.gmail.com"
      type="cite">
      <div dir="ltr"><br>
        <div class="gmail_extra">
          <div class="gmail_quote">On Tue, Nov 22, 2016 at 4:28 PM,
            Zoran Stojsavljevic <span dir="ltr"><<a
                moz-do-not-send="true"
                href="mailto:zoran.stojsavljevic@gmail.com"
                target="_blank">zoran.stojsavljevic@gmail.com</a>></span>
            wrote:<br>
            <blockquote class="gmail_quote" style="margin:0px 0px 0px
              0.8ex;border-left:1px solid
              rgb(204,204,204);padding-left:1ex">
              <div dir="ltr">
                <div class="gmail_extra">
                  <div class="gmail_quote"><span class="gmail-"></span>If
                    MCU is later, could you, please, explain how you did
                    this in IVB Coreboot code (since this might be
                    beneficial to Federico's attempts)?</div>
                </div>
              </div>
            </blockquote>
            <div><br>
            </div>
            <div>Edit devicetree.cb and set:<br>
              <br>
              ┬áregister "max_mem_clock_mhz" = "666"<br>
            </div>
          </div>
        </div>
      </div>
    </blockquote>
    I've looked inside `src/mainboard/lenovo/x201/devicetree.cb` but the
    option "max_mem_clock_mhz" is missing,<br>
    while it is present in other sandy bridge mainboards.<br>
    So I think the actual `raminit.c` of nehalem does not allow choosing
    a fixed frequency for RAM.<br>
    <br>
    <blockquote
cite="mid:CA+=e9eM2Z+azRLC72hwbhQN765X2U_m6j3RYKcN8wHO2bh+_LQ@mail.gmail.com"
      type="cite">
      <div dir="ltr">
        <div class="gmail_extra">
          <div class="gmail_quote">
            <blockquote class="gmail_quote" style="margin:0px 0px 0px
              0.8ex;border-left:1px solid
              rgb(204,204,204);padding-left:1ex">
              <div dir="ltr">
                <div class="gmail_extra">
                  <div class="gmail_quote">
                    <div>Here I understood that you tried to compare IVB
                      raminit.c source code with MRC algorithm, embedded
                      in BIOS itself. And I have here one ignorant
                      question: what is the difference between IVB (I
                      assumed in this case SNB (tock), since I could not
                      find IVB (tick) in rc/northbridge/intel/)
                      raminit.c source code and MRC from IVB BIOS (there
                      MUST be some difference, it is obvious, doesn't
                      it)?</div>
                  </div>
                </div>
              </div>
            </blockquote>
            <div><br>
            </div>
            <div>I suppose there is one. I don't know. I want to
              investigate. I will certainly try again by adding the
              patches suggested by Kyosti. As soon as I can get the MRC
              blob to work, I can make some better guesses about what is
              going wrong (I tried so many various things already) by
              having some reference points.<br>
            </div>
          </div>
        </div>
      </div>
    </blockquote>
    About trying with MRC blob RAM init, sadly the source file
    `raminit_mrc.c` present for SNB is absent from
    `src/northbridge/intel/nehalem`<br>
    So I think MRC blob init has not been coded/is not supported in
    nehalem :(<br>
    This is confirmed by this wiki page:
    <a class="moz-txt-link-freetext" href="https://www.coreboot.org/Intel_Native_Raminit">https://www.coreboot.org/Intel_Native_Raminit</a><br>
    <br>
    So the options of fixing frequency or using MRC are not feasible on
    nehalem at the moment.<br>
    I will try to check the RAM settings running the Lenovo bios and see
    if i can add the code for "max_mem_clock_mhz"<br>
    Unfortunately I won't be able to flash coreboot until friday because
    my laptop needs an external power supply for the flash chip<br>
    and I will borrow it on friday.<br>
    <br>
    Thanks again,<br>
    Federico<br>
    <br>
  </body>
</html>