[coreboot] SPI controller and Lock bits

Sam Kuper sam.kuper at uclmail.net
Sat Sep 29 22:59:18 CEST 2018


On 29/09/2018, ron minnich <rminnich at gmail.com> wrote:
> It's not a screw in Chromebooks any more, see vadim's excellent OSFC.io
> talk on how it works now.

Vadim Bendebury? This talk below?

https://osfc.io/talks/google-secure-microcontroller-and-ccd-closed-case-debugging

If so, is there a video or audio recording available? Thanks.

> I think the momentary switch would not be acceptable to anyone for cost

Small momentary switches cost pennies and laptops usually have about a
hundred of them fitted, of various kinds. (Power on/off/suspend;
volume up/down; keyboard keys; maybe others.) So, fitting laptops with
momentary switches is definitely acceptable to manufacturers.

> and reliability reasons.

Such switches are often rated for ~100,000 cycles. It seems unlikely
that any laptop or its owner would live long enough to flash the ROM
chip even close to 100,000 times. So, I don't anticipate a reliability
problem.

> The way chromebooks do the protection now is really well done.

I look forward to reading Vadim's slides, and perhaps also to watching
or listening to his talk. Thanks for the pointer.



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