[coreboot] Wired problems with Intel skylake based board

Peter Stuge peter at stuge.se
Tue Sep 25 12:26:20 CEST 2018

Christian Gmeiner wrote:
> Most of the time the system works as expected but from time to rebooting
> the system fails completely.

Only ever when rebooting, or does cold boot also fail sometimes?

(Make a test system to cold boot your system in a loop.)

> there are two FPGAs connected via PCIe to the system where one is used
> to reset the system. The reset is done via SYS_RESET#.

Are the FPGAs also reset by that?

If yes, how long do they need to initialize to where HDL acts
correctly on PCIe?

If no, how long do they need to move from resetting the system to
where HDL acts correctly on PCIe for the newly resetted platform?

> Now I run into different kind of issues:
> - pcie link training fails from time to time

On both links, or only one of them? Can you tell?

> - looks like PLTRST# of the sunrisepoint pch holds the system in reset
>   for minutes.

I don't know if there's enough PCH documentation to know exactly why
it would do that - but I can imagine that it holds reset as long as
some conditions are not met, I can also imagine that the FPGAs cause
some undefined PCIe behavior in the PCH which happens to get it stuck
in reset for a while.

> Are there any hints to debug my issues?

As always, try to isolate the problem.

Can you completely remove one or ideally both FPGAs from the equation?

You mention that one of them is used for reset. At least disable the
other one, destructively if need be.


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