October 2018 Archives by date

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Starting: Mon Oct 1 07:13:24 CEST 2018
Ending: Wed Oct 31 14:37:20 CET 2018
Messages: 188

[coreboot] 8GB graphics cards work on coreboot - in case anyone is wondering Taiidan at gmx.com
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Jose Trujillo
[coreboot] Porting coreboot to another Intel's bay-trail Jose Trujillo
[coreboot] microcode blob or ascii Jose Trujillo
[coreboot] SPI controller and Lock bits Youness Alaoui
[coreboot] SPI controller and Lock bits Youness Alaoui
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] SPI controller and Lock bits Sam Kuper
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] SPI controller and Lock bits Martin Kepplinger
[coreboot] SPI controller and Lock bits Sam Kuper
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] SPI controller and Lock bits Martin Kepplinger
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] SPI controller and Lock bits Peter Stuge
[coreboot] microcode blob or ascii galla rao
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Zvi Vered
[coreboot] removing bounce buffers ron minnich
[coreboot] removing bounce buffers Nico Huber
[coreboot] SPI controller and Lock bits Sam Kuper
[coreboot] removing bounce buffers ron minnich
[coreboot] intel/i82801dx SMM memory size? ron minnich
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Jose Trujillo
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Mariusz Szafrański
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] USB 2.0 EHCI debug dongle doesn't print logs (at Lenovo G505S) Nico Huber
[coreboot] removing bounce buffers Peter Stuge
[coreboot] [skylake] Can not turn monitor on Zheng Bao
[coreboot] microcode blob or ascii Jose Trujillo
[coreboot] [skylake] Can not turn monitor on Nico Huber
[coreboot] lower memory performance with coreboot on KGPE-D16 Iru Cai
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Jose Trujillo
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Zvi Vered
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Jose Trujillo
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. fightfakenews
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. Patrick Georgi
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. David Hendricks
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. seclists at boxdan.com
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Zvi Vered
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. Lance Zhao
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Zvi Vered
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. Jonathan Neuschäfer
[coreboot] Is this fake news or not? Bloomberg says China is using a rice-sized chip to hack amazon servers. Mike Banon
[coreboot] SPI controller and Lock bits Martin Kepplinger
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Jose Trujillo
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Mariusz Szafrański
[coreboot] SPI controller and Lock bits Nico Huber
[coreboot] New Defects reported by Coverity Scan for coreboot scan-admin at coverity.com
[coreboot] [skylake] Can not turn monitor on Zheng Bao
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Zvi Vered
[coreboot] lower memory performance with coreboot on KGPE-D16 Daniel Kulesz
[coreboot] [skylake] Can not turn monitor on Nico Huber
[coreboot] [skylake] Can not turn monitor on Matt DeVillier
[coreboot] [skylake] Can not turn monitor on Zheng Bao
[coreboot] Source code for "Intel Firmware" Zvi Vered
[coreboot] [skylake] Can not turn monitor on Nico Huber
[coreboot] Source code for "Intel Firmware" Nathaniel Roach
[coreboot] Burn 2MB coreboot.rom on 8MB flash chip Nico Huber
[coreboot] Source code for "Intel Firmware" Nico Huber
[coreboot] current state of board/f2a85m kinky_nekoboi
[coreboot] Source code for "Intel Firmware" Zvi Vered
[coreboot] Source code for "Intel Firmware" Angel Pons
[coreboot] Source code for "Intel Firmware" Nico Huber
[coreboot] Source code for "Intel Firmware" ron minnich
[coreboot] Source code for "Intel Firmware" Zvi Vered
[coreboot] current state of board/f2a85m David Hendricks
[coreboot] Source code for "Intel Firmware" Andrew Luke Nesbit
[coreboot] Source code for "Intel Firmware" ron minnich
[coreboot] Source code for "Intel Firmware" Andrew Luke Nesbit
[coreboot] Source code for "Intel Firmware" ron minnich
[coreboot] Bootblock CMOS default and the checksum algo William McCall
[coreboot] lower memory performance with coreboot on KGPE-D16 Iru Cai
[coreboot] Bootblock CMOS default and the checksum algo Lance Zhao
[coreboot] Bootblock CMOS default and the checksum algo William McCall
[coreboot] Source code for "Intel Firmware" Philipp Stanner
[coreboot] Source code for "Intel Firmware" Nico Huber
[coreboot] Change superio in "Bayley Bay FSP-based CRB" Zvi Vered
[coreboot] Source code for "Intel Firmware" Merlin Büge
[coreboot] Change superio in "Bayley Bay FSP-based CRB" Jose Trujillo
[coreboot] USB 2.0 EHCI debug dongle doesn't print logs (at Lenovo G505S) Denis 'GNUtoo' Carikli
[coreboot] Lenovo G505S - spkmodem console sound, is correct? Please listen and tell Denis 'GNUtoo' Carikli
[coreboot] Lenovo G505S - spkmodem console sound, is correct? Please listen and tell Denis 'GNUtoo' Carikli
[coreboot] Change superio in "Bayley Bay FSP-based CRB" Zvi Vered
[coreboot] New Defects reported by Coverity Scan for coreboot scan-admin at coverity.com
[coreboot] Source code for "Intel Firmware" Philipp Stanner
[coreboot] post code 0xb0 after coreboot.rom BIOs burn Zvi Vered
[coreboot] Source code for "Intel Firmware" Peter Stuge
[coreboot] Watchdog timer (WDT) support on Kabylake w/FSP2.0 Matt DeVillier
[coreboot] Post code 0xCE: coreboot.rom with fsp Zvi Vered
[coreboot] MRC in coreboot Antony AbeePrakash X V
[coreboot] Wired problems with Intel skylake based board Christian Gmeiner
[coreboot] intel/i82801dx SMM memory size? Kyösti Mälkki
[coreboot] MRC in coreboot Aaron Durbin
[coreboot] MRC in coreboot Antony AbeePrakash X V
[coreboot] MRC in coreboot Aaron Durbin
[coreboot] Wired problems with Intel skylake based board Nico Huber
[coreboot] MRC in coreboot Antony AbeePrakash X V
[coreboot] MRC in coreboot Aaron Durbin
[coreboot] New Defects reported by Coverity Scan for coreboot scan-admin at coverity.com
[coreboot] Source code for "Intel Firmware" Philipp Stanner
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Zvi Vered
[coreboot] Source code for "Intel Firmware" Nico Huber
[coreboot] Source code for "Intel Firmware" ron minnich
[coreboot] Source code for "Intel Firmware" Nico Huber
[coreboot] Source code for "Intel Firmware" Peter Stuge
[coreboot] Source code for "Intel Firmware" Philipp Stanner
[coreboot] Source code for "Intel Firmware" Nico Huber
[coreboot] What determines PCI-e capabilities per chipset in coreboot? (ie: pcie register space) Taiidan at gmx.com
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Jose Trujillo
[coreboot] Watchdog timer (WDT) support on Kabylake w/FSP2.0 Solanki, Naresh
[coreboot] Wired problems with Intel skylake based board Christian Gmeiner
[coreboot] MRC in coreboot Antony AbeePrakash X V
[coreboot] Wired problems with Intel skylake based board Naresh G. Solanki
[coreboot] MRC in coreboot Aaron Durbin
[coreboot] SPI controller and Lock bits Youness Alaoui
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Zvi Vered
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Jose Trujillo
[coreboot] Wired problems with Intel skylake based board Christian Gmeiner
[coreboot] Wired problems with Intel skylake based board Peter Stuge
[coreboot] MRC in coreboot Peter Stuge
[coreboot] Wired problems with Intel skylake based board Christian Gmeiner
[coreboot] Wired problems with Intel skylake based board Naresh G. Solanki
[coreboot] Wired problems with Intel skylake based board Nico Huber
[coreboot] Wired problems with Intel skylake based board Nico Huber
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Zvi Vered
[coreboot] SPI controller and Lock bits Sam Kuper
[coreboot] SPI controller and Lock bits Peter Stuge
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Jose Trujillo
[coreboot] SPI controller and Lock bits R S
[coreboot] SPI controller and Lock bits Youness Alaoui
[coreboot] Modifying FSP in Binary Configuration Tool (BCT) Zvi Vered
[coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU? Taiidan at gmx.com
[coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU? Angel Pons
[coreboot] FSP integration Zvi Vered
[coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU? Nico Huber
[coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU? Angel Pons
[coreboot] New Defects reported by Coverity Scan for coreboot scan-admin at coverity.com
[coreboot] F2A85M board kinky_nekoboi
[coreboot] T520 vs. T530 yc-153434 at hs-weingarten.de
[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Zheng Bao
[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Marc Jones
[coreboot] T520 vs. T530 Iru Cai
[coreboot] Contribution to coreboot board status Sven Dreyer
[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Rudolf Marek
[coreboot] Contribution to coreboot board status Patrick Georgi
[coreboot] T520 vs. T530 Michał Kopeć
[coreboot] T520 vs. T530 Nico Huber
[coreboot] T520 vs. T530 Evgeny Zinoviev
[coreboot] T520 vs. T530 Michał Kopeć
[coreboot] T520 vs. T530 Evgeny Zinoviev
[coreboot] T520 vs. T530 Nico Huber
[coreboot] Contribution to coreboot board status Sven Dreyer
[coreboot] Basic bios info mad.scientist.at.large at tutanota.com
[coreboot] Basic bios info Jose Trujillo
[coreboot] Basic bios info Jose Trujillo
[coreboot] cbfstool issue Wim Vervoorn
[coreboot] Basic bios info Nico Huber
[coreboot] Basic bios info mad.scientist.at.large at tutanota.com
[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Zheng Bao
[coreboot] uefi rootkit (lojax) szbnwer at gmail.com
[coreboot] Reducing FSP performance time Antony AbeePrakash X V
[coreboot] Hardware diagnostic yanvasilij yan
[coreboot] New Defects reported by Coverity Scan for coreboot scan-admin at coverity.com
[coreboot] Hardware diagnostic Naresh G. Solanki
[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Rudolf Marek
[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Zheng Bao
[coreboot] Hardware diagnostic Peter Stuge
[coreboot] Hardware diagnostic Nico Huber
[coreboot] Matrix instead (or additionally to) IRC Philipp Stanner
[coreboot] Matrix instead (or additionally to) IRC Luc Verhaegen
[coreboot] Matrix instead (or additionally to) IRC Patrick Georgi
[coreboot] Matrix instead (or additionally to) IRC Timothy Pearson
[coreboot] Matrix instead (or additionally to) IRC Philipp Stanner
[coreboot] Matrix instead (or additionally to) IRC Iru Cai
[coreboot] Revisiting an old project from the FreeBIOS days Gregg Levine
[coreboot] Matrix instead (or additionally to) IRC Duncan Guthrie
[coreboot] Matrix instead (or additionally to) IRC Timothy Pearson
[coreboot] Matrix instead (or additionally to) IRC Angel Pons
[coreboot] Reducing FSP performance time Nico Huber
[coreboot] Reducing FSP performance time Antony AbeePrakash X V
[coreboot] Reducing FSP performance time Nico Huber
[coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM: Jose Trujillo
[coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM: Lance Zhao
[coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM: Jose Trujillo
[coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM: Lance Zhao
[coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM: Jose Trujillo
[coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM: Jose Trujillo

Last message date: Wed Oct 31 14:37:20 CET 2018
Archived on: Wed Oct 31 15:00:07 CET 2018

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