[coreboot] Wired problems with Intel skylake based board

Naresh G. Solanki naresh.solanki.2011 at gmail.com
Tue Oct 16 15:16:34 CEST 2018


Hi,

A1. PLTRST# not getting de-asserted might be a separate issue. I
recommend you debug power on sequence & find the exact point of
failures like powerok, VR stability(check for over/undervoltage) near
SoC.
A2. Do same VR's provide power to FPGA & there is no power shortage ?

B1. SoC is clocked by external crystal, Can you please check Crystal
OSC frequency, accuracy/deviation from expected values. I'm guessing
that the external crystal frequency is around 8% lower than expected
levels.
B2. If possible provide waveform of external crystal & clksrc

Regards,
Naresh G Solanki
On Tue, Oct 16, 2018 at 3:13 PM Christian Gmeiner
<christian.gmeiner at gmail.com> wrote:
>
> Am Di., 16. Okt. 2018 um 11:25 Uhr schrieb Peter Stuge <peter at stuge.se>:
> >
> > Christian Gmeiner wrote:
> > > The system does not hang if I only change
> > >
> > >     mem_cfg->PegDisableSpreadSpectrumClocking = 1;
> > >
> > > But it has no effect on the PCIe reference clock and it looks like
> > > spread spectrum is still used.
> >
> > AFAIK Peg refers to PCI Express Graphics. Maybe there's another,
> > per-port, setting?
> >
>
> Could be but and the comment is about this variable is wrong:
> https://github.com/coreboot/coreboot/blob/f3122426b851b9ca009e501a8d8c60d062f84c98/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h#L534
>
> --
> greets
> --
> Christian Gmeiner, MSc
>
> https://christian-gmeiner.info
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot



-- 
Best regards,
Naresh G. Solanki



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