[coreboot] Modifying FSP in Binary Configuration Tool (BCT)

Zvi Vered veredz72 at gmail.com
Tue Oct 16 05:41:47 CEST 2018

Hi Jose, All,

According to the following outputs,  it seems my target has SPD EEPROM.
If I understand correctly from your reply, I should modify only:
DRAM Speed: 1333 MT/s
DIMM 0 Enable: Enabled
DIMM 1 Enable: Disabled
DIMM_DWidth: x8
DIMM_Density: ??? (Default is 2Gbit)
DIMM_BusWidth: 64
DIMM_Sides: 1 Ranks

Am I right ?

I tried booting the target with the modified FSP and got post code : 0xCE
There is nothing on the 232 console.
There is no such post code in coreboot code.
Is it possible that FSP is sending post code ?
How can I proceed from here?

Thank you very much,

********************************** sensors-detect
Probing for `SPD EEPROM'...                                 Yes
    (confidence 8, not a hardware monitoring chip)
********************************** dmidecode
Handle 0x0009, DMI type 17, 34 bytes
Memory Device
Array Handle: 0x0008
Error Information Handle: Not Provided
Total Width: 72 bits
Data Width: 64 bits
Size: 4096 MB
Form Factor: SODIMM
Set: None
Locator: DIMM0
Bank Locator: BANK 0
Type: DDR3
Type Detail: Synchronous
Speed: 1333 MHz
Manufacturer: 00
Serial Number: 00000000
Asset Tag: Unknown
Part Number:
Rank: Unknown
Configured Clock Speed: 1333 MHz

Handle 0x000B, DMI type 17, 34 bytes
Memory Device
Array Handle: 0x0008
Error Information Handle: Not Provided
Total Width: Unknown
Data Width: Unknown
Size: No Module Installed
Form Factor: SODIMM
Set: None
Locator: DIMM1
Bank Locator: BANK 1
Type: Unknown
Type Detail: None
Speed: Unknown
Manufacturer: Not Specified
Serial Number: Not Specified
Asset Tag: Unknown
Part Number: Not Specified
Rank: Unknown
Configured Clock Speed: Unknown
# decode-dimms version 6231 (2014-02-20 10:54:34 +0100)

Memory Serial Presence Detect Decoder
By Philip Edelbrock, Christian Zuckschwerdt, Burkart Lingner,
Jean Delvare, Trent Piepho and others

Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/8-0050
Guessing DIMM is in                             bank 1

---=== SPD EEPROM Information ===---
EEPROM CRC of bytes 0-116                       OK (0x59A6)
# of bytes written to SDRAM EEPROM              176
Total number of bytes in EEPROM                 256
Fundamental Memory type                         DDR3 SDRAM
Module Type                                     72b-SO-UDIMM

---=== Memory Characteristics ===---
Fine time base                                  1.000 ps
Medium time base                                0.125 ns
Maximum module speed                            1333 MHz (PC3-10600)
Size                                            4096 MB
Banks x Rows x Columns x Bits                   8 x 16 x 10 x 64
Ranks                                           1
SDRAM Device Width                              8 bits
Bus Width Extension                             8 bits
tCL-tRCD-tRP-tRAS                               9-9-9-24
Supported CAS Latencies (tCL)                   10T, 9T, 8T, 7T, 6T

---=== Timing Parameters ===---
Minimum Write Recovery time (tWR)               15.000 ns
Minimum Row Active to Row Active Delay (tRRD)   6.000 ns
Minimum Active to Auto-Refresh Delay (tRC)      49.125 ns
Minimum Recovery Delay (tRFC)                   260.000 ns
Minimum Write to Read CMD Delay (tWTR)          7.500 ns
Minimum Read to Pre-charge CMD Delay (tRTP)     7.500 ns
Minimum Four Activate Window Delay (tFAW)       30.000 ns

---=== Optional Features ===---
Operable voltages                               1.5V, 1.35V
RZQ/6 supported?                                Yes
RZQ/7 supported?                                Yes
DLL-Off Mode supported?                         Yes
Operating temperature range                     0-95 degrees C
Refresh Rate in extended temp range             1X
Auto Self-Refresh?                              No
On-Die Thermal Sensor readout?                  No
Partial Array Self-Refresh?                     No
Thermal Sensor Accuracy                         Not implemented
SDRAM Device Type                               Standard Monolithic

---=== Manufacturer Data ===---
Module Manufacturer                             Invalid
Part Number                                     Undefined

Number of SDRAM DIMMs detected and decoded: 1

On Mon, Oct 15, 2018 at 9:43 AM Jose Trujillo <ce.autom at protonmail.com>

> Zvika:
> In my experience with my Baytrail system I can tell you my system is
> "really" memory down because has soldered memory chips on the motherboard
> BUT has also a soldered SPD memory so, if keep "Enable Memory Down =
> Disabled" in BCT the system fetch memory timings from SPD so, no need to
> edit memory timings but other things like "DRAM Speed" and "DRAM Type" and
> other settings (not timings) needs to be edited.
> but if still needed to edit timings extract them from SPD with
> "i2c-tools-perl".... I alredy sent you this information in previous emails
> and attachments so, look for this.....
> Good luck,
> Jose.
> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> On Friday, October 12, 2018 7:29 PM, Zvi Vered <veredz72 at gmail.com> wrote:
> > Hello,
> >
> > The BCT has a "Memory Down" section.
> > Can you please advise how can I know the right values for my board ?
> >
> > DIMM 0/1 Enable:
> > DIMM DWidth:
> > DIMM Density:
> > DIMM_BusWidth:
> > DIMM Sides:
> > tCL:
> > tRP_tRCD:
> > tWR:
> > tWTR:
> > tRRD:
> > tRTP:
> > tFAW:
> >
> > Thank you in advance,
> > Zvika
> >
> >
> -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> >
> > coreboot mailing list: coreboot at coreboot.org
> > https://mail.coreboot.org/mailman/listinfo/coreboot
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