[coreboot] What determines PCI-e capabilities per chipset in coreboot? (ie: pcie register space)

Taiidan at gmx.com Taiidan at gmx.com
Sun Oct 14 23:36:22 CEST 2018

What I want to do is fix the SR5690/SR56xx capabilities list to reflect
what is actually documented rather than what currently functions.

It is lacking ARI, ATS and a few other things although it has ACS I am
not sure exactly what enables it at the moment either coreboot or
quirked in linux.

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