[coreboot] Modifying FSP in Binary Configuration Tool (BCT)

[Jose Trujillo]

Zvika:

In my experience with my Baytrail system I can tell you my system is "really" memory down because has soldered memory chips on the motherboard BUT has also a soldered SPD memory so, if keep "Enable Memory Down = Disabled" in BCT the system fetch memory timings from SPD so, no need to edit memory timings but other things like "DRAM Speed" and "DRAM Type" and other settings (not timings) needs to be edited.

but if still needed to edit timings extract them from SPD with "i2c-tools-perl".... I alredy sent you this information in previous emails and attachments so, look for this.....

Good luck,
Jose.

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Friday, October 12, 2018 7:29 PM, Zvi Vered <veredz72 at gmail.com> wrote:

> Hello,
>
> The BCT has a "Memory Down" section.
> Can you please advise how can I know the right values for my board ?
>
> DIMM 0/1 Enable:
> DIMM DWidth:
> DIMM Density:
> DIMM_BusWidth:
> DIMM Sides:
> tCL:
> tRP_tRCD:
> tWR:
> tWTR:
> tRRD:
> tRTP:
> tFAW:
>
> Thank you in advance,
> Zvika
>
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