[coreboot] Wired problems with Intel skylake based board

Nico Huber nico.h at gmx.de
Fri Oct 12 10:15:45 CEST 2018


On 10/11/18 11:29 AM, Christian Gmeiner wrote:
> During the last weeks I found the root cause of my problem - PCIe
> spread spectrum
> 
> Our FPGAs need a stable 100MHz PCIE clock to work. The used FSP config
> thing looked
> like this:
> 
> void mainboard_memory_init_params(FSPM_UPD *mupd)
> {
>     FSP_M_CONFIG *mem_cfg;
>     struct spd_block blk = {
>         .addr_map = { 0x50 },
>     };
> 
>     mem_cfg = &mupd->FspmConfig;
> 
>     mem_cfg->PegDisableSpreadSpectrumClocking = 1;
>     mem_cfg->PchPmPciePllSsc = 0;
> 
>     ...
> }
> 
> With this configuration the PCIe reference clock was off more then 8% which
> caused the system to hang during cold and warm boots.
> 
> In the next step I removed assignment of PchPmPciePllSsc as it is documented
> as 'No BIOS override'. With this change I got more then 1000 soft and
> 2000 hard reboots
> without any problem. Keep in mind we started with only 10 successful reboots.

Please be more specific about the final setting of this UPD. `No BIOS
override` is the documentation for the default value of 0xff. But is
this set to the default in the binary? who knows...

> 
> The big problem is that PegDisableSpreadSpectrumClocking has no effect
> at all. I measured
> the freq it is not the 100MHz as expected. And I need to have a stable
> 100MHz this clock source
> is used internally by the FPGA to drive internal clocks. The end
> results is that EtherCAT is not
> able to sync.

This setting is about a different clock, I guess. Can you please clarify
what is connected to which clock on your board.

Nico



More information about the coreboot mailing list