[coreboot] Coreboot and Kabylake FSP-M

[Jose Trujillo]

Hello Roman,

You need to provide the serial dump logs because I think very little amount of people here has access to the list of FSP post codes for every processor family (may be I am wrong but so far I don't know of someone who has them).

Which coreboot platform are you using?

Jose

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‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Thursday, November 29, 2018 6:09 PM, roman perepelitsin <perepelitsin.roman at gmail.com> wrote:

> Hi!
> I'm try to run Coreboot on Intel Xeon1505L with C236 and DDR4 memory down using kabylake FSP GOLD. I setup UART0 for coreboot console out and try to set UART0 for FSP-M debug out, but have only POST codes to port80/81 from FSP-M. In FSP integration guide I didn't find full POST-codes describe.
> So - can some body help with this? My lasts post codes: DD46h DD30h DD32h DD35h DD45h DD36h DD37h DD41h DD4Dh DD3fh. I think it MRC codes, but that they mean - don't know. I see in oscilloscope, that DDR try to start in this stage, but after all I have error from FSP-M 80000007h.
>
> --
> regards,
> Perepelitsin Roman
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