[coreboot] GSOC submission
tpearson at raptorengineering.com
Thu Nov 29 23:07:53 CET 2018
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On the POWER9 topic, it might even be possible to skip QEMU and go
straight to hardware. My current understanding is that the FSI drivers
in OpenBMC allow single stepping of the CPU and dumping of registers,
without any other hardware being required to access those features.
There's also a built-in firmware-from-RAM loader on the BMC side, so
iterating changes should be fairly easy.
Raptor would be also willing to donate a number of POWER9 development
kits in support of a coreboot port, if there's interest.
On 11/29/2018 08:13 AM, Patrick Georgi via coreboot wrote:
> I was planning to apply this year, let's see what comes of it.
> Thank you for the list of project ideas, very valuable!
> Am Do., 29. Nov. 2018 um 15:04 Uhr schrieb Arthur Heymans
> <arthur at aheymans.xyz <mailto:arthur at aheymans.xyz>>:
> It has been a few years since coreboot (or flashrom) applied for Google
> Summer Of Code. In 2019 the applications for organizations open on
> january 2019 and student applications on March 25.
> I think it would be great if the coreboot project could apply in 2019,
> as doing so has been very valuable for the project in the past.
> I don't really know the full set of requirements and procedures, but I
> think it could be worthwhile to start thinking about project ideas.
> A few ideas were already suggested on IRC on freenode #coreboot:
> - 64bit x86 ramstage (hard)
> - documented microcode update methods and write a tool that generates a
> webpage which microcodes are included in coreboot (easy)
> - nvidea optimus support (medium)
> - QEMU power9 support / initial openpower support (hard I guess?)
> - Rework device resource allocation to support 64bit BAR (relatively
> Any ideas or suggestions?
> Kind regards
> Arthur Heymans
> coreboot mailing list: coreboot at coreboot.org
> <mailto:coreboot at coreboot.org>
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