[coreboot] GSOC submission

Taiidan at gmx.com Taiidan at gmx.com
Thu Nov 29 22:13:36 CET 2018

On 11/29/2018 09:02 AM, Arthur Heymans wrote:
> Hi
> It has been a few years since coreboot (or flashrom) applied for Google
> Summer Of Code. In 2019 the applications for organizations open on
> january 2019 and student applications on March 25.
> I think it would be great if the coreboot project could apply in 2019,
> as doing so has been very valuable for the project in the past.
> I don't really know the full set of requirements and procedures, but I
> think it could be worthwhile to start thinking about project ideas.
> A few ideas were already suggested on IRC on freenode #coreboot:
> - 64bit x86 ramstage (hard)
> - documented microcode update methods and write a tool that generates a
> webpage which microcodes are included in coreboot (easy)
> - nvidea optimus support (medium)
> - QEMU power9 support / initial openpower support (hard I guess?)

IMO not worth it since TALOS 2/Blackbird already have owner controlled
open source firmware directly from the factory so do various other
OpenPOWER machines.

> - Rework device resource allocation to support 64bit BAR (relatively
> hard)

Agreed this would be super great. I get plenty of failed to assign BAR
errors on my coreboot machines and my system doesn't work properly due
to not enough BAR space unless the PCI-e cards are inserted in a
specific order.

> Any ideas or suggestions?

* SR-IOV/ARI support on the SR56xx AMD chipset code fam15h native init
coreboot so boards KGPE-D16/KCMA-D8.

According to the chipset documentation the chipsets support it and
various other advanced PCI-e features that aren't activated so it should
be easy but I can't figure out how to do it.

* Activating the IOMMU in coreboot on boards that support it.

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