[coreboot] [SMSC SCH3114] Super I/O issues
lynxis at fe80.eu
Fri Nov 16 15:48:29 CET 2018
the IRQ are usually freely configurable via the LDN.
Using the lower bits of 0x70h is quite common to select the IRQ.
The SuperIO is connected via LPC, which supports all legacy IRQs by
Further, depending on the Chipset, it must allow to receive the IRQs
over the SerIRQ line of the LPC.
mail: lynxis at fe80.eu
jabber: lynxis at fe80.eu
gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Size: 833 bytes
Desc: OpenPGP digital signature
More information about the coreboot