[coreboot] FSP settings according to decode-dimms

[Zvi Vered]

Hi Nico, All,

The DRAM is soldered. There is no DIMM module.
After changing to "Enable Memory Down  = Enabled" I got post code 0x92 just
before calling to:
FspInitApi(&FspInitParams) in src/drivers/intel/fsp1_0

>From there,  romstage_main_continue in soc/intel/fsp_baytrail/romstage
should be called but it does not happen.
Any ideas why ?

Thank you,
Zvika

On Sat, Nov 10, 2018 at 2:01 PM Nico Huber <nico.h at gmx.de> wrote:

> Hi Zvi,
>
> I assume you still ask for the BayTrail FSP, correct? You didn't
> mention it in your last mails.
>
> On 11/10/18 8:47 AM, Zvi Vered wrote:
> > Module Type                                     72b-SO-UDIMM
>
> This suggests that you have a DIMM? i.e. a module, not soldered down
> DRAM, is that correct?
>
> > Enable Memory Down: Disabled
> > DRAM Speed: 1333
> > ...
>
> These settings all live in a struct called MEMORY_DOWN_DATA. I don't
> know for sure, but I assume with "EnableMemoryDown Disabled" you disable
> the whole struct. I can also not find a single board in coreboot that
> sets `EnableMemoryDown` explicitly to 0.
>
> Maybe one of the FSP BayTrail maintainers can clarify? or even provide
> some documentation?
>
> Also, please use coreboot's infrastructure to set these things from your
> mainboard's `romstage.c` or `devicetree.cb`. If you want help with BCT,
> better ask Intel.
>
> If you have a real DIMM module with an SPD that can be read from SMBus,
> I would try setting `PcdMrcInitSPDAddr1`. Be aware that it expects the
> SMBus address shifted left by 1 (e.g. the 7-bit address 0x50 would be
> 0xa0 for FSP). You can set it from the devicetree, for examples check
> the source, e.g.:
>   git grep '"PcdMrcInitSPDAddr1"'
>
> If you don't have a module but soldered down memory, here's an example
> how to map the values from your SPD to FSP: `mainboard/siemens/mc_tcu3/
> romstage.c`.
>
> I'm not sure if this works though, as this board also sets
> `PcdMrcInitSPDAddr*` in the devicetree, which confuses me (same for
> intel/minnowmax, Intel maintainers?).
>
> Hope that helps,
> Nico
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20181111/9c5f9305/attachment.html>