[coreboot] New Defects reported by Coverity Scan for coreboot

scan-admin at coverity.com scan-admin at coverity.com
Tue Nov 6 15:41:09 CET 2018


Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

6 new defect(s) introduced to coreboot found with Coverity Scan.


New defect(s) Reported-by: Coverity Scan
Showing 6 of 6 defect(s)


** CID 1396579:    (STRAY_SEMICOLON)
/src/soc/mediatek/mt8183/auxadc.c: 46 in auxadc_get_rawdata()
/src/soc/mediatek/mt8183/auxadc.c: 49 in auxadc_get_rawdata()
/src/soc/mediatek/mt8183/auxadc.c: 53 in auxadc_get_rawdata()


________________________________________________________________________________________________________
*** CID 1396579:    (STRAY_SEMICOLON)
/src/soc/mediatek/mt8183/auxadc.c: 46 in auxadc_get_rawdata()
40     	assert(!expired);					\
41     })
42     
43     static uint32_t auxadc_get_rawdata(int channel)
44     {
45     	setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
>>>     CID 1396579:    (STRAY_SEMICOLON)
>>>     A "while" statement with no block followed by a stand-alone block is suspicious.
46     	wait_ms(!(read32(&mtk_auxadc->con2) & 0x1), 300);
47     
48     	clrbits_le32(&mtk_auxadc->con1, 1 << channel);
49     	wait_ms(!(read32(&mtk_auxadc->data[channel]) & (1 << 12)), 300);
50     
51     	setbits_le32(&mtk_auxadc->con1, 1 << channel);
/src/soc/mediatek/mt8183/auxadc.c: 49 in auxadc_get_rawdata()
43     static uint32_t auxadc_get_rawdata(int channel)
44     {
45     	setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
46     	wait_ms(!(read32(&mtk_auxadc->con2) & 0x1), 300);
47     
48     	clrbits_le32(&mtk_auxadc->con1, 1 << channel);
>>>     CID 1396579:    (STRAY_SEMICOLON)
>>>     A "while" statement with no block followed by a stand-alone block is suspicious.
49     	wait_ms(!(read32(&mtk_auxadc->data[channel]) & (1 << 12)), 300);
50     
51     	setbits_le32(&mtk_auxadc->con1, 1 << channel);
52     	udelay(25);
53     	wait_ms(read32(&mtk_auxadc->data[channel]) & (1 << 12), 300);
54     
/src/soc/mediatek/mt8183/auxadc.c: 53 in auxadc_get_rawdata()
47     
48     	clrbits_le32(&mtk_auxadc->con1, 1 << channel);
49     	wait_ms(!(read32(&mtk_auxadc->data[channel]) & (1 << 12)), 300);
50     
51     	setbits_le32(&mtk_auxadc->con1, 1 << channel);
52     	udelay(25);
>>>     CID 1396579:    (STRAY_SEMICOLON)
>>>     A "while" statement with no block followed by a stand-alone block is suspicious.
53     	wait_ms(read32(&mtk_auxadc->data[channel]) & (1 << 12), 300);
54     
55     	uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF;
56     
57     	setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10);
58     

** CID 1396578:    (UNINIT)
/src/arch/riscv/trap_handler.c: 98 in interrupt_handler()
/src/arch/riscv/trap_handler.c: 100 in interrupt_handler()
/src/arch/riscv/trap_handler.c: 102 in interrupt_handler()
/src/arch/riscv/trap_handler.c: 104 in interrupt_handler()
/src/arch/riscv/trap_handler.c: 106 in interrupt_handler()
/src/arch/riscv/trap_handler.c: 107 in interrupt_handler()


________________________________________________________________________________________________________
*** CID 1396578:    (UNINIT)
/src/arch/riscv/trap_handler.c: 98 in interrupt_handler()
92     
93     		clear_csr(mie, MIP_MTIP);
94     		set_csr(mip, MIP_STIP);
95     
96     		break;
97     	case IRQ_M_SOFT:
>>>     CID 1396578:    (UNINIT)
>>>     Using uninitialized value "sp".
98     		if (HLS()->ipi_pending & IPI_SOFT) {
99     			set_csr(mip, MIP_SSIP);
100     		} else if (HLS()->ipi_pending & IPI_FENCE_I) {
101     			asm volatile("fence.i");
102     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA) {
103     			asm volatile("sfence.vma");
/src/arch/riscv/trap_handler.c: 100 in interrupt_handler()
94     		set_csr(mip, MIP_STIP);
95     
96     		break;
97     	case IRQ_M_SOFT:
98     		if (HLS()->ipi_pending & IPI_SOFT) {
99     			set_csr(mip, MIP_SSIP);
>>>     CID 1396578:    (UNINIT)
>>>     Using uninitialized value "sp".
100     		} else if (HLS()->ipi_pending & IPI_FENCE_I) {
101     			asm volatile("fence.i");
102     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA) {
103     			asm volatile("sfence.vma");
104     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) {
105     			asm volatile("sfence.vma");
/src/arch/riscv/trap_handler.c: 102 in interrupt_handler()
96     		break;
97     	case IRQ_M_SOFT:
98     		if (HLS()->ipi_pending & IPI_SOFT) {
99     			set_csr(mip, MIP_SSIP);
100     		} else if (HLS()->ipi_pending & IPI_FENCE_I) {
101     			asm volatile("fence.i");
>>>     CID 1396578:    (UNINIT)
>>>     Using uninitialized value "sp".
102     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA) {
103     			asm volatile("sfence.vma");
104     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) {
105     			asm volatile("sfence.vma");
106     		} else if (HLS()->ipi_pending & IPI_SHUTDOWN) {
107     			while (HLS()->ipi_pending & IPI_SHUTDOWN)
/src/arch/riscv/trap_handler.c: 104 in interrupt_handler()
98     		if (HLS()->ipi_pending & IPI_SOFT) {
99     			set_csr(mip, MIP_SSIP);
100     		} else if (HLS()->ipi_pending & IPI_FENCE_I) {
101     			asm volatile("fence.i");
102     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA) {
103     			asm volatile("sfence.vma");
>>>     CID 1396578:    (UNINIT)
>>>     Using uninitialized value "sp".
104     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) {
105     			asm volatile("sfence.vma");
106     		} else if (HLS()->ipi_pending & IPI_SHUTDOWN) {
107     			while (HLS()->ipi_pending & IPI_SHUTDOWN)
108     				asm volatile("wfi");
109     		}
/src/arch/riscv/trap_handler.c: 106 in interrupt_handler()
100     		} else if (HLS()->ipi_pending & IPI_FENCE_I) {
101     			asm volatile("fence.i");
102     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA) {
103     			asm volatile("sfence.vma");
104     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) {
105     			asm volatile("sfence.vma");
>>>     CID 1396578:    (UNINIT)
>>>     Using uninitialized value "sp".
106     		} else if (HLS()->ipi_pending & IPI_SHUTDOWN) {
107     			while (HLS()->ipi_pending & IPI_SHUTDOWN)
108     				asm volatile("wfi");
109     		}
110     		break;
111     	default:
/src/arch/riscv/trap_handler.c: 107 in interrupt_handler()
101     			asm volatile("fence.i");
102     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA) {
103     			asm volatile("sfence.vma");
104     		} else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) {
105     			asm volatile("sfence.vma");
106     		} else if (HLS()->ipi_pending & IPI_SHUTDOWN) {
>>>     CID 1396578:    (UNINIT)
>>>     Using uninitialized value "sp".
107     			while (HLS()->ipi_pending & IPI_SHUTDOWN)
108     				asm volatile("wfi");
109     		}
110     		break;
111     	default:
112     		printk(BIOS_EMERG, "======================================\n");

** CID 1396577:    (UNINIT)
/src/arch/riscv/smp.c: 35 in smp_pause()
/src/arch/riscv/smp.c: 41 in smp_pause()
/src/arch/riscv/smp.c: 48 in smp_pause()
/src/arch/riscv/smp.c: 52 in smp_pause()
/src/arch/riscv/smp.c: 53 in smp_pause()
/src/arch/riscv/smp.c: 58 in smp_pause()
/src/arch/riscv/smp.c: 61 in smp_pause()
/src/arch/riscv/smp.c: 62 in smp_pause()


________________________________________________________________________________________________________
*** CID 1396577:    (UNINIT)
/src/arch/riscv/smp.c: 35 in smp_pause()
29     	int hartid = read_csr(mhartid);
30     
31     	if (hartid != working_hartid) {
32     		/* waiting for work hart */
33     		do {
34     			barrier();
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
35     		} while (SYNCA != 0x01234567);
36     
37     		clear_csr(mstatus, MSTATUS_MIE);
38     		write_csr(mie, MIP_MSIP);
39     
40     		/* count how many cores enter the halt */
/src/arch/riscv/smp.c: 41 in smp_pause()
35     		} while (SYNCA != 0x01234567);
36     
37     		clear_csr(mstatus, MSTATUS_MIE);
38     		write_csr(mie, MIP_MSIP);
39     
40     		/* count how many cores enter the halt */
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
41     		__sync_fetch_and_add(&SYNCB, 1);
42     
43     		do {
44     			barrier();
45     			__asm__ volatile ("wfi");
46     		} while ((read_csr(mip) & MIP_MSIP) == 0);
/src/arch/riscv/smp.c: 48 in smp_pause()
42     
43     		do {
44     			barrier();
45     			__asm__ volatile ("wfi");
46     		} while ((read_csr(mip) & MIP_MSIP) == 0);
47     		set_msip(hartid, 0);
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
48     		HLS()->entry.fn(HLS()->entry.arg);
49     	} else {
50     		/* Initialize the counter and
51     		 * mark the work hart into smp_pause */
52     		SYNCB = 0;
53     		SYNCA = 0x01234567;
/src/arch/riscv/smp.c: 52 in smp_pause()
46     		} while ((read_csr(mip) & MIP_MSIP) == 0);
47     		set_msip(hartid, 0);
48     		HLS()->entry.fn(HLS()->entry.arg);
49     	} else {
50     		/* Initialize the counter and
51     		 * mark the work hart into smp_pause */
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
52     		SYNCB = 0;
53     		SYNCA = 0x01234567;
54     
55     		/* waiting for other Hart to enter the halt */
56     		do {
57     			barrier();
/src/arch/riscv/smp.c: 53 in smp_pause()
47     		set_msip(hartid, 0);
48     		HLS()->entry.fn(HLS()->entry.arg);
49     	} else {
50     		/* Initialize the counter and
51     		 * mark the work hart into smp_pause */
52     		SYNCB = 0;
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
53     		SYNCA = 0x01234567;
54     
55     		/* waiting for other Hart to enter the halt */
56     		do {
57     			barrier();
58     		} while (SYNCB + 1 < CONFIG_RISCV_HART_NUM);
/src/arch/riscv/smp.c: 58 in smp_pause()
52     		SYNCB = 0;
53     		SYNCA = 0x01234567;
54     
55     		/* waiting for other Hart to enter the halt */
56     		do {
57     			barrier();
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
58     		} while (SYNCB + 1 < CONFIG_RISCV_HART_NUM);
59     
60     		/* initialize for the next call */
61     		SYNCA = 0;
62     		SYNCB = 0;
63     	}
/src/arch/riscv/smp.c: 61 in smp_pause()
55     		/* waiting for other Hart to enter the halt */
56     		do {
57     			barrier();
58     		} while (SYNCB + 1 < CONFIG_RISCV_HART_NUM);
59     
60     		/* initialize for the next call */
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
61     		SYNCA = 0;
62     		SYNCB = 0;
63     	}
64     #undef SYNCA
65     #undef SYNCB
66     }
/src/arch/riscv/smp.c: 62 in smp_pause()
56     		do {
57     			barrier();
58     		} while (SYNCB + 1 < CONFIG_RISCV_HART_NUM);
59     
60     		/* initialize for the next call */
61     		SYNCA = 0;
>>>     CID 1396577:    (UNINIT)
>>>     Using uninitialized value "sp".
62     		SYNCB = 0;
63     	}
64     #undef SYNCA
65     #undef SYNCB
66     }
67     

** CID 1396576:    (UNINIT)
/src/arch/riscv/smp.c: 76 in smp_resume()
/src/arch/riscv/smp.c: 77 in smp_resume()
/src/arch/riscv/smp.c: 84 in smp_resume()


________________________________________________________________________________________________________
*** CID 1396576:    (UNINIT)
/src/arch/riscv/smp.c: 76 in smp_resume()
70     	int hartid = read_csr(mhartid);
71     
72     	if (fn == NULL)
73     		die("must pass a non-null function pointer\n");
74     
75     	for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) {
>>>     CID 1396576:    (UNINIT)
>>>     Using uninitialized value "sp".
76     		OTHER_HLS(i)->entry.fn = fn;
77     		OTHER_HLS(i)->entry.arg = arg;
78     	}
79     
80     	for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)
81     		if (i != hartid)
82     			set_msip(i, 1);
83     
84     	HLS()->entry.fn(HLS()->entry.arg);
/src/arch/riscv/smp.c: 77 in smp_resume()
71     
72     	if (fn == NULL)
73     		die("must pass a non-null function pointer\n");
74     
75     	for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) {
76     		OTHER_HLS(i)->entry.fn = fn;
>>>     CID 1396576:    (UNINIT)
>>>     Using uninitialized value "sp".
77     		OTHER_HLS(i)->entry.arg = arg;
78     	}
79     
80     	for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)
81     		if (i != hartid)
82     			set_msip(i, 1);
83     
84     	HLS()->entry.fn(HLS()->entry.arg);
/src/arch/riscv/smp.c: 84 in smp_resume()
78     	}
79     
80     	for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)
81     		if (i != hartid)
82     			set_msip(i, 1);
83     
>>>     CID 1396576:    (UNINIT)
>>>     Using uninitialized value "sp".
84     	HLS()->entry.fn(HLS()->entry.arg);

** CID 1396575:  Uninitialized variables  (UNINIT)
/src/arch/riscv/sbi.c: 44 in sbi_set_timer()


________________________________________________________________________________________________________
*** CID 1396575:  Uninitialized variables  (UNINIT)
/src/arch/riscv/sbi.c: 44 in sbi_set_timer()
38     }
39     
40     static uintptr_t sbi_set_timer(uint64_t when)
41     {
42     	clear_csr(mip, MIP_STIP);
43     	set_csr(mie, MIP_MTIP);
>>>     CID 1396575:  Uninitialized variables  (UNINIT)
>>>     Using uninitialized value "sp".
44     	*(HLS()->timecmp) = when;
45     	return 0;
46     }
47     
48     #if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
49     static uintptr_t sbi_console_putchar(uint8_t ch)

** CID 1396574:  Uninitialized variables  (UNINIT)
/src/arch/riscv/sbi.c: 31 in send_ipi()


________________________________________________________________________________________________________
*** CID 1396574:  Uninitialized variables  (UNINIT)
/src/arch/riscv/sbi.c: 31 in send_ipi()
25     
26     static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type)
27     {
28     	uintptr_t mask = mprv_read_uintptr_t(pmask);
29     	for (int i = 0; mask; i++) {
30     		if (mask & 1) {
>>>     CID 1396574:  Uninitialized variables  (UNINIT)
>>>     Using uninitialized value "sp".
31     			OTHER_HLS(i)->ipi_pending |= type;
32     			/* send soft interrupt to target hart */
33     			set_msip(i, 1);
34     		}
35     		mask = mask >> 1;
36     	}


________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbLuoVetFLSjdonCi1EjfHRqWGQvojmmkYaBE-2BPJiTQvQ-3D-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5a31m51VEsEaxFt1YGbyr6wNWh1JRkzG6iEWnu4wa11R6V6bq3pvRdnRMNLGWgttGAab8saZW-2BgimLNQFi615pGDzotKysOu2G2J4DGnZTtorDLvESCDRCTODv3O77-2B7n1VYt5e-2BYXktmH9OM-2FL42YRQ224IXfqqi-2BMUaEbYo2-2F2Afr5Jd9JHIIEpLZPsm1PcE-3D




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