[coreboot] Non-working PS/2 on KGPE-D16
Piotr Kubaj
pkubaj at anongoth.pl
Fri May 18 23:17:07 CEST 2018
Hi,
I'd like to use PS/2 ports in my KGPE-D16. That's why I want to connect my mouse and keyboard to it (and free USB ports). Both mouse and keyboard have USB plugs (I use adapters), but I have also old PS/2 keyboard used for tests.
The problem is that neither mouse nor keyboard work with coreboot (both work with stock BIOS). I set CONFIG_SEABIOS_PS2_TIMEOUT=3000 in coreboot config. I use SeaBIOS with default config and verified that it contains CONFIG_PS2PORT=y (both configs extracted from rom are attached).
I use coreboot tag 4.8.1.
I also attach serial log with debug_level Spew and SeaBIOS debug level 7 (which adds PS/2 related entries). Could anyone help me trace this issue?
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coreboot-4.8.1-6794ce02d45273427c1c6675950c8468380c040a Fri May 18 18:53:13 UTC 2018 romstage starting...
Initial stack pointer: 000dffb8
CPU APICID 00 start flag set
BSP Family_Model: 00600f20
*sysinfo range: [000c2d40,000cd2ac]
bsp_apicid = 00
cpu_init_detectedx = 00000000
sb700 reset flags: 0004
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'microcode_amd.bin'
CBFS: Found @ offset a04c0 size 318c
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'microcode_amd_fam15h.bin'
CBFS: Found @ offset a36c0 size 1ec4
[microcode] patch id to apply = 0x06000832
[microcode] updated to patch id = 0x06000832 success
cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done
Enter amd_ht_init
AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Forcing HT links to isochronous mode due to enabled IOMMU
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Exit amd_ht_init
amd_ht_fixup
amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
cpuSetAMDPCI 00 done
cpuSetAMDPCI 01 done
cpuSetAMDPCI 02 done
cpuSetAMDPCI 03 done
Prep FID/VID Node:00
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f1c
F3xD8: 03000016
F3xDC: 05475635
Prep FID/VID Node:01
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f1c
F3xD8: 03000016
F3xDC: 05475635
Prep FID/VID Node:02
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f1c
F3xD8: 03000016
F3xDC: 05475635
Prep FID/VID Node:03
F3x80: e20be281
F3x84: 01e200e2
F3xD4: c3312f1c
F3xD8: 03000016
F3xDC: 05475635
setup_remote_node: 01 done
Start node 01 done.
setup_remote_node: 02 done
Start node 02 done.
setup_remote_node: 03 done
Start node 03 done.
core0 started: 01 02 03
sr5650_early_setup()
get_cpu_rev EAX=0x600f20.
CPU Rev is Fam 15.
NB Revision is A12.
fam10_optimization()
sr5650_por_init
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Enabling IOMMU
sb700_early_setup()
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A15
sb700_devices_por_init: Disabling ISA DMA support
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
sb700_pmio_por_init()
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00 cores: 07 pass 1
Start other core - nodeid: 00 cores: 07
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
init node: 01 cores: 07 pass 1
Start other core - nodeid: 01 cores: 07
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
init node: 02 cores: 07 pass 1
Start other core - nodeid: 02 cores: 07
get_boot_apic_id: using 34 as APIC ID for node 2, core 2
get_boot_apic_id: using 36 as APIC ID for node 2, core 4
get_boot_apic_id: using 38 as APIC ID for node 2, core 6
init node: 03 cores: 07 pass 1
Start other core - nodeid: 03 cores: 07
get_boot_apic_id: using 42 as APIC ID for node 3, core 2
get_boot_apic_id: using 44 as APIC ID for node 3, core 4
get_boot_apic_id: using 46 as APIC ID for node 3, core 6
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02started
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03started
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04started
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05started
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
* AP 06started
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
* AP 07started
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
* AP 09started
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
* AP 0astarted
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
* AP 0bstarted
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
* AP 0cstarted
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
* AP 0dstarted
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
* AP 0estarted
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
* AP 0fstarted
get_boot_apic_id: using 33 as APIC ID for node 2, core 1
* AP 21started
get_boot_apic_id: using 34 as APIC ID for node 2, core 2
* AP 22started
get_boot_apic_id: using 35 as APIC ID for node 2, core 3
* AP 23started
get_boot_apic_id: using 36 as APIC ID for node 2, core 4
* AP 24started
get_boot_apic_id: using 37 as APIC ID for node 2, core 5
* AP 25started
get_boot_apic_id: using 38 as APIC ID for node 2, core 6
* AP 26started
get_boot_apic_id: using 39 as APIC ID for node 2, core 7
* AP 27started
get_boot_apic_id: using 41 as APIC ID for node 3, core 1
* AP 29started
get_boot_apic_id: using 42 as APIC ID for node 3, core 2
* AP 2astarted
get_boot_apic_id: using 43 as APIC ID for node 3, core 3
* AP 2bstarted
get_boot_apic_id: using 44 as APIC ID for node 3, core 4
* AP 2cstarted
get_boot_apic_id: using 45 as APIC ID for node 3, core 5
* AP 2dstarted
get_boot_apic_id: using 46 as APIC ID for node 3, core 6
* AP 2estarted
get_boot_apic_id: using 47 as APIC ID for node 3, core 7
* AP 2fstarted
Begin FIDVID MSR 0xc0010071 0x52c6009e 0x40024a0c
End FIDVIDMSR 0xc0010071 0x52c6009e 0x40024a0c
sr5650_htinit: Node 0 Link 1, HT freq=e.
sr5650_htinit: HT3 mode
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01stopped
get_boot_apic_id: using 2 as APIC ID for node 0, core 2
* AP 02stopped
get_boot_apic_id: using 3 as APIC ID for node 0, core 3
* AP 03stopped
get_boot_apic_id: using 4 as APIC ID for node 0, core 4
* AP 04stopped
get_boot_apic_id: using 5 as APIC ID for node 0, core 5
* AP 05stopped
get_boot_apic_id: using 6 as APIC ID for node 0, core 6
* AP 06stopped
get_boot_apic_id: using 7 as APIC ID for node 0, core 7
* AP 07stopped
get_boot_apic_id: using 9 as APIC ID for node 1, core 1
* AP 09stopped
get_boot_apic_id: using 10 as APIC ID for node 1, core 2
* AP 0astopped
get_boot_apic_id: using 11 as APIC ID for node 1, core 3
* AP 0bstopped
get_boot_apic_id: using 12 as APIC ID for node 1, core 4
* AP 0cstopped
get_boot_apic_id: using 13 as APIC ID for node 1, core 5
* AP 0dstopped
get_boot_apic_id: using 14 as APIC ID for node 1, core 6
* AP 0estopped
get_boot_apic_id: using 15 as APIC ID for node 1, core 7
* AP 0fstopped
get_boot_apic_id: using 33 as APIC ID for node 2, core 1
* AP 21stopped
get_boot_apic_id: using 34 as APIC ID for node 2, core 2
* AP 22stopped
get_boot_apic_id: using 35 as APIC ID for node 2, core 3
* AP 23stopped
get_boot_apic_id: using 36 as APIC ID for node 2, core 4
* AP 24stopped
get_boot_apic_id: using 37 as APIC ID for node 2, core 5
* AP 25stopped
get_boot_apic_id: using 38 as APIC ID for node 2, core 6
* AP 26stopped
get_boot_apic_id: using 39 as APIC ID for node 2, core 7
* AP 27stopped
get_boot_apic_id: using 41 as APIC ID for node 3, core 1
* AP 29stopped
get_boot_apic_id: using 42 as APIC ID for node 3, core 2
* AP 2astopped
get_boot_apic_id: using 43 as APIC ID for node 3, core 3
* AP 2bstopped
get_boot_apic_id: using 44 as APIC ID for node 3, core 4
* AP 2cstopped
get_boot_apic_id: using 45 as APIC ID for node 3, core 5
* AP 2dstopped
get_boot_apic_id: using 46 as APIC ID for node 3, core 6
* AP 2estopped
get_boot_apic_id: using 47 as APIC ID for node 3, core 7
* AP 2fstopped
fill_mem_ctrl() detected 4 nodes
Timestamp - before ram initialization: 5399744308
raminit_amdmct()
raminit_amdmct begin:
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_preInitDCT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
DIMMPresence: DIMMValid=8
DIMMPresence: DIMMPresent=8
DIMMPresence: RegDIMMPresent=8
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=8
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=8
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=8
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=0
DIMMPresence: MAload[0]=0
DIMMPresence: MAdimms[0]=0
DIMMPresence: DATAload[1]=2
DIMMPresence: MAload[1]=20
DIMMPresence: MAdimms[1]=1
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 01
enable_spd_node1()
mctAutoInitMCT_D: mct_preInitDCT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
DIMMPresence: DIMMValid=0
DIMMPresence: DIMMPresent=0
DIMMPresence: RegDIMMPresent=0
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=0
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=0
DIMMPresence: MAload[0]=0
DIMMPresence: MAdimms[0]=0
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2000
DIMMPresence: ErrStatus 1
DIMMPresence: ErrCode 2
DIMMPresence: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 02
enable_spd_node2()
mctAutoInitMCT_D: mct_preInitDCT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
DIMMPresence: DIMMValid=4
DIMMPresence: DIMMPresent=4
DIMMPresence: RegDIMMPresent=4
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=4
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=4
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=4
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=20
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2005
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTPreInit_D: mct_DIMMPresence Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 03
enable_spd_node3()
mctAutoInitMCT_D: mct_preInitDCT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
DIMMPresence: DIMMValid=0
DIMMPresence: DIMMPresent=0
DIMMPresence: RegDIMMPresent=0
DIMMPresence: LRDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=0
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=0
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=0
DIMMPresence: MAload[0]=0
DIMMPresence: MAdimms[0]=0
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 2000
DIMMPresence: ErrStatus 1
DIMMPresence: ErrCode 2
DIMMPresence: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D: DIMMSetVoltage
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Node 00 DIMM voltage set to index 00
Node 01 DIMM voltage set to index 00
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 00
enable_spd_node0()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 6
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 2
AutoCycTiming: Done
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 1 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 01
enable_spd_node1()
mctAutoInitMCT_D: mct_initDCT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
SPDCalcWidth: Status 2000
SPDCalcWidth: ErrStatus 1
SPDCalcWidth: ErrCode 2
SPDCalcWidth: Done
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 02
enable_spd_node2()
mctAutoInitMCT_D: mct_initDCT
SPDCalcWidth: Status 2005
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 6
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 00112222
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramControlReg_Init_D: Start
mct_DramControlReg_Init_D: F2xA8: 00000c00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
mct_DramControlReg_Init_D: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: mctSMBhub_Init
activate_spd_rom() for node 03
enable_spd_node3()
mctAutoInitMCT_D: mct_initDCT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
SPDCalcWidth: Status 2000
SPDCalcWidth: ErrStatus 1
SPDCalcWidth: ErrCode 2
SPDCalcWidth: Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3ffffff BottomIO: c00000
Node: 00 base: 03 limit: 43fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 4400000 limit: 83fffff BottomIO: c00000
Node: 02 base: 4400003 limit: 83fffff
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
Copy dram map from Node 0 to Node 01
Copy dram map from Node 0 to Node 02
Copy dram map from Node 0 to Node 03
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 1
phyAssistedMemFnceTraining: done training node 0 DCT 1
phyAssistedMemFnceTraining: training node 2 DCT 0
phyAssistedMemFnceTraining: done training node 2 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 1: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 1: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 0041
Lane 01 initial seed: 0041
Lane 02 initial seed: 0041
Lane 03 initial seed: 0041
Lane 04 initial seed: 0041
Lane 05 initial seed: 0041
Lane 06 initial seed: 0041
Lane 07 initial seed: 0041
Lane 08 initial seed: 0041
Lane 00 nibble 0 raw readback: 003f
Lane 00 nibble 0 adjusted value (pre nibble): 003f
Lane 00 nibble 0 adjusted value (post nibble): 003f
Lane 01 nibble 0 raw readback: 003c
Lane 01 nibble 0 adjusted value (pre nibble): 003c
Lane 01 nibble 0 adjusted value (post nibble): 003c
Lane 02 nibble 0 raw readback: 003a
Lane 02 nibble 0 adjusted value (pre nibble): 003a
Lane 02 nibble 0 adjusted value (post nibble): 003a
Lane 03 nibble 0 raw readback: 0038
Lane 03 nibble 0 adjusted value (pre nibble): 0038
Lane 03 nibble 0 adjusted value (post nibble): 0038
Lane 04 nibble 0 raw readback: 002f
Lane 04 nibble 0 adjusted value (pre nibble): 002f
Lane 04 nibble 0 adjusted value (post nibble): 002f
Lane 05 nibble 0 raw readback: 0031
Lane 05 nibble 0 adjusted value (pre nibble): 0031
Lane 05 nibble 0 adjusted value (post nibble): 0031
Lane 06 nibble 0 raw readback: 0034
Lane 06 nibble 0 adjusted value (pre nibble): 0034
Lane 06 nibble 0 adjusted value (post nibble): 0034
Lane 07 nibble 0 raw readback: 0037
Lane 07 nibble 0 adjusted value (pre nibble): 0037
Lane 07 nibble 0 adjusted value (post nibble): 0037
Lane 08 nibble 0 raw readback: 002f
Lane 08 nibble 0 adjusted value (pre nibble): 002f
Lane 08 nibble 0 adjusted value (post nibble): 002f
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
activate_spd_rom() for node 01
enable_spd_node1()
activate_spd_rom() for node 02
enable_spd_node2()
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 initial seed: 0041
Lane 01 initial seed: 0041
Lane 02 initial seed: 0041
Lane 03 initial seed: 0041
Lane 04 initial seed: 0041
Lane 05 initial seed: 0041
Lane 06 initial seed: 0041
Lane 07 initial seed: 0041
Lane 08 initial seed: 0041
Lane 00 nibble 0 raw readback: 004c
Lane 00 nibble 0 adjusted value (pre nibble): 004c
Lane 00 nibble 0 adjusted value (post nibble): 004c
Lane 01 nibble 0 raw readback: 0047
Lane 01 nibble 0 adjusted value (pre nibble): 0047
Lane 01 nibble 0 adjusted value (post nibble): 0047
Lane 02 nibble 0 raw readback: 0045
Lane 02 nibble 0 adjusted value (pre nibble): 0045
Lane 02 nibble 0 adjusted value (post nibble): 0045
Lane 03 nibble 0 raw readback: 0042
Lane 03 nibble 0 adjusted value (pre nibble): 0042
Lane 03 nibble 0 adjusted value (post nibble): 0042
Lane 04 nibble 0 raw readback: 003a
Lane 04 nibble 0 adjusted value (pre nibble): 003a
Lane 04 nibble 0 adjusted value (post nibble): 003a
Lane 05 nibble 0 raw readback: 003d
Lane 05 nibble 0 adjusted value (pre nibble): 003d
Lane 05 nibble 0 adjusted value (post nibble): 003d
Lane 06 nibble 0 raw readback: 003f
Lane 06 nibble 0 adjusted value (pre nibble): 003f
Lane 06 nibble 0 adjusted value (post nibble): 003f
Lane 07 nibble 0 raw readback: 0042
Lane 07 nibble 0 adjusted value (pre nibble): 0042
Lane 07 nibble 0 adjusted value (post nibble): 0042
Lane 08 nibble 0 raw readback: 003b
Lane 08 nibble 0 adjusted value (pre nibble): 003b
Lane 08 nibble 0 adjusted value (post nibble): 003b
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
activate_spd_rom() for node 03
enable_spd_node3()
fam15_receiver_enable_training_seed: using seed: 004d
fam15_receiver_enable_training_seed: using seed: 004d
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
fam15_receiver_enable_training_seed: using seed: 0054
fam15_receiver_enable_training_seed: using seed: 0054
TrainRcvrEn: Status 2005
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 1 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 1
phyAssistedMemFnceTraining: done training node 0 DCT 1
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 1: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 1: Done
Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0047
Lane 00 new seed: 0047
Lane 01 scaled delay: 0047
Lane 01 new seed: 0047
Lane 02 scaled delay: 0047
Lane 02 new seed: 0047
Lane 03 scaled delay: 0047
Lane 03 new seed: 0047
Lane 04 scaled delay: 0047
Lane 04 new seed: 0047
Lane 05 scaled delay: 0047
Lane 05 new seed: 0047
Lane 06 scaled delay: 0047
Lane 06 new seed: 0047
Lane 07 scaled delay: 0047
Lane 07 new seed: 0047
Lane 08 scaled delay: 0047
Lane 08 new seed: 0047
Lane 00 nibble 0 raw readback: 0046
Lane 00 nibble 0 adjusted value (pre nibble): 0046
Lane 00 nibble 0 adjusted value (post nibble): 0046
Lane 01 nibble 0 raw readback: 0043
Lane 01 nibble 0 adjusted value (pre nibble): 0043
Lane 01 nibble 0 adjusted value (post nibble): 0043
Lane 02 nibble 0 raw readback: 003f
Lane 02 nibble 0 adjusted value (pre nibble): 003f
Lane 02 nibble 0 adjusted value (post nibble): 003f
Lane 03 nibble 0 raw readback: 003c
Lane 03 nibble 0 adjusted value (pre nibble): 003c
Lane 03 nibble 0 adjusted value (post nibble): 003c
Lane 04 nibble 0 raw readback: 0032
Lane 04 nibble 0 adjusted value (pre nibble): 0032
Lane 04 nibble 0 adjusted value (post nibble): 0032
Lane 05 nibble 0 raw readback: 0034
Lane 05 nibble 0 adjusted value (pre nibble): 0034
Lane 05 nibble 0 adjusted value (post nibble): 0034
Lane 06 nibble 0 raw readback: 0038
Lane 06 nibble 0 adjusted value (pre nibble): 0038
Lane 06 nibble 0 adjusted value (post nibble): 0038
Lane 07 nibble 0 raw readback: 003b
Lane 07 nibble 0 adjusted value (pre nibble): 003b
Lane 07 nibble 0 adjusted value (post nibble): 003b
Lane 08 nibble 0 raw readback: 0034
Lane 08 nibble 0 adjusted value (pre nibble): 0034
Lane 08 nibble 0 adjusted value (post nibble): 0034
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 1 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 1
phyAssistedMemFnceTraining: done training node 0 DCT 1
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 1: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 1: Done
Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0052
Lane 00 new seed: 0052
Lane 01 scaled delay: 004e
Lane 01 new seed: 004e
Lane 02 scaled delay: 0049
Lane 02 new seed: 0049
Lane 03 scaled delay: 0045
Lane 03 new seed: 0045
Lane 04 scaled delay: 0037
Lane 04 new seed: 0037
Lane 05 scaled delay: 003a
Lane 05 new seed: 003a
Lane 06 scaled delay: 003f
Lane 06 new seed: 003f
Lane 07 scaled delay: 0043
Lane 07 new seed: 0043
Lane 08 scaled delay: 003a
Lane 08 new seed: 003a
Lane 00 nibble 0 raw readback: 0053
Lane 00 nibble 0 adjusted value (pre nibble): 0053
Lane 00 nibble 0 adjusted value (post nibble): 0053
Lane 01 nibble 0 raw readback: 004f
Lane 01 nibble 0 adjusted value (pre nibble): 004f
Lane 01 nibble 0 adjusted value (post nibble): 004f
Lane 02 nibble 0 raw readback: 004a
Lane 02 nibble 0 adjusted value (pre nibble): 004a
Lane 02 nibble 0 adjusted value (post nibble): 004a
Lane 03 nibble 0 raw readback: 0046
Lane 03 nibble 0 adjusted value (pre nibble): 0046
Lane 03 nibble 0 adjusted value (post nibble): 0046
Lane 04 nibble 0 raw readback: 0038
Lane 04 nibble 0 adjusted value (pre nibble): 0038
Lane 04 nibble 0 adjusted value (post nibble): 0038
Lane 05 nibble 0 raw readback: 003c
Lane 05 nibble 0 adjusted value (pre nibble): 003c
Lane 05 nibble 0 adjusted value (post nibble): 003c
Lane 06 nibble 0 raw readback: 0040
Lane 06 nibble 0 adjusted value (pre nibble): 0040
Lane 06 nibble 0 adjusted value (post nibble): 0040
Lane 07 nibble 0 raw readback: 0044
Lane 07 nibble 0 adjusted value (pre nibble): 0044
Lane 07 nibble 0 adjusted value (post nibble): 0044
Lane 08 nibble 0 raw readback: 003a
Lane 08 nibble 0 adjusted value (pre nibble): 003a
Lane 08 nibble 0 adjusted value (post nibble): 003a
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 1 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 1
phyAssistedMemFnceTraining: done training node 0 DCT 1
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 1: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 1: Done
Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 005f
Lane 00 new seed: 005f
Lane 01 scaled delay: 005a
Lane 01 new seed: 005a
Lane 02 scaled delay: 0054
Lane 02 new seed: 0054
Lane 03 scaled delay: 004f
Lane 03 new seed: 004f
Lane 04 scaled delay: 003e
Lane 04 new seed: 003e
Lane 05 scaled delay: 0043
Lane 05 new seed: 0043
Lane 06 scaled delay: 0048
Lane 06 new seed: 0048
Lane 07 scaled delay: 004d
Lane 07 new seed: 004d
Lane 08 scaled delay: 0040
Lane 08 new seed: 0040
Lane 00 nibble 0 raw readback: 005f
Lane 00 nibble 0 adjusted value (pre nibble): 005f
Lane 00 nibble 0 adjusted value (post nibble): 005f
Lane 01 nibble 0 raw readback: 005b
Lane 01 nibble 0 adjusted value (pre nibble): 005b
Lane 01 nibble 0 adjusted value (post nibble): 005b
Lane 02 nibble 0 raw readback: 0056
Lane 02 nibble 0 adjusted value (pre nibble): 0056
Lane 02 nibble 0 adjusted value (post nibble): 0056
Lane 03 nibble 0 raw readback: 0051
Lane 03 nibble 0 adjusted value (pre nibble): 0051
Lane 03 nibble 0 adjusted value (post nibble): 0051
Lane 04 nibble 0 raw readback: 003f
Lane 04 nibble 0 adjusted value (pre nibble): 003f
Lane 04 nibble 0 adjusted value (post nibble): 003f
Lane 05 nibble 0 raw readback: 0044
Lane 05 nibble 0 adjusted value (pre nibble): 0044
Lane 05 nibble 0 adjusted value (post nibble): 0044
Lane 06 nibble 0 raw readback: 004a
Lane 06 nibble 0 adjusted value (pre nibble): 004a
Lane 06 nibble 0 adjusted value (post nibble): 004a
Lane 07 nibble 0 raw readback: 004f
Lane 07 nibble 0 adjusted value (pre nibble): 004f
Lane 07 nibble 0 adjusted value (post nibble): 004f
Lane 08 nibble 0 raw readback: 0042
Lane 08 nibble 0 adjusted value (pre nibble): 0042
Lane 08 nibble 0 adjusted value (post nibble): 0042
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0012
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 1 timing/termination pattern 00363936 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 0 DCT 1
phyAssistedMemFnceTraining: done training node 0 DCT 1
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 1: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 1: Done
Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0
mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 3
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 3
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 3
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
DIMM 1 RttWr: 0
DIMM 1 RttNom: 3
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
DIMM 1 RttWr: 0
Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 006b
Lane 00 new seed: 006b
Lane 01 scaled delay: 0066
Lane 01 new seed: 0066
Lane 02 scaled delay: 0060
Lane 02 new seed: 0060
Lane 03 scaled delay: 005a
Lane 03 new seed: 005a
Lane 04 scaled delay: 0045
Lane 04 new seed: 0045
Lane 05 scaled delay: 004b
Lane 05 new seed: 004b
Lane 06 scaled delay: 0052
Lane 06 new seed: 0052
Lane 07 scaled delay: 0058
Lane 07 new seed: 0058
Lane 08 scaled delay: 0048
Lane 08 new seed: 0048
Lane 00 nibble 0 raw readback: 002e
Lane 00 nibble 0 adjusted value (pre nibble): 006e
Lane 00 nibble 0 adjusted value (post nibble): 006e
Lane 01 nibble 0 raw readback: 0027
Lane 01 nibble 0 adjusted value (pre nibble): 0067
Lane 01 nibble 0 adjusted value (post nibble): 0067
Lane 02 nibble 0 raw readback: 0020
Lane 02 nibble 0 adjusted value (pre nibble): 0060
Lane 02 nibble 0 adjusted value (post nibble): 0060
Lane 03 nibble 0 raw readback: 005c
Lane 03 nibble 0 adjusted value (pre nibble): 005c
Lane 03 nibble 0 adjusted value (post nibble): 005c
Lane 04 nibble 0 raw readback: 0046
Lane 04 nibble 0 adjusted value (pre nibble): 0046
Lane 04 nibble 0 adjusted value (post nibble): 0046
Lane 05 nibble 0 raw readback: 004c
Lane 05 nibble 0 adjusted value (pre nibble): 004c
Lane 05 nibble 0 adjusted value (post nibble): 004c
Lane 06 nibble 0 raw readback: 0052
Lane 06 nibble 0 adjusted value (pre nibble): 0052
Lane 06 nibble 0 adjusted value (post nibble): 0052
Lane 07 nibble 0 raw readback: 0058
Lane 07 nibble 0 adjusted value (pre nibble): 0058
Lane 07 nibble 0 adjusted value (post nibble): 0058
Lane 08 nibble 0 raw readback: 0049
Lane 08 nibble 0 adjusted value (pre nibble): 0049
Lane 08 nibble 0 adjusted value (post nibble): 0049
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 3
Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098
DIMM 1 RttWr: 0
DIMM 1 RttNom: 3
Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098
DIMM 1 RttWr: 0
activate_spd_rom() for node 01
enable_spd_node1()
activate_spd_rom() for node 02
enable_spd_node2()
SetTargetFreq: Start
SetTargetFreq: Node 2: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 10112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 2 DCT 0
phyAssistedMemFnceTraining: done training node 2 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0047
Lane 00 new seed: 0047
Lane 01 scaled delay: 0047
Lane 01 new seed: 0047
Lane 02 scaled delay: 0047
Lane 02 new seed: 0047
Lane 03 scaled delay: 0047
Lane 03 new seed: 0047
Lane 04 scaled delay: 0047
Lane 04 new seed: 0047
Lane 05 scaled delay: 0047
Lane 05 new seed: 0047
Lane 06 scaled delay: 0047
Lane 06 new seed: 0047
Lane 07 scaled delay: 0047
Lane 07 new seed: 0047
Lane 08 scaled delay: 0047
Lane 08 new seed: 0047
Lane 00 nibble 0 raw readback: 0050
Lane 00 nibble 0 adjusted value (pre nibble): 0050
Lane 00 nibble 0 adjusted value (post nibble): 0050
Lane 01 nibble 0 raw readback: 004a
Lane 01 nibble 0 adjusted value (pre nibble): 004a
Lane 01 nibble 0 adjusted value (post nibble): 004a
Lane 02 nibble 0 raw readback: 0047
Lane 02 nibble 0 adjusted value (pre nibble): 0047
Lane 02 nibble 0 adjusted value (post nibble): 0047
Lane 03 nibble 0 raw readback: 0045
Lane 03 nibble 0 adjusted value (pre nibble): 0045
Lane 03 nibble 0 adjusted value (post nibble): 0045
Lane 04 nibble 0 raw readback: 003a
Lane 04 nibble 0 adjusted value (pre nibble): 003a
Lane 04 nibble 0 adjusted value (post nibble): 003a
Lane 05 nibble 0 raw readback: 003f
Lane 05 nibble 0 adjusted value (pre nibble): 003f
Lane 05 nibble 0 adjusted value (post nibble): 003f
Lane 06 nibble 0 raw readback: 0040
Lane 06 nibble 0 adjusted value (pre nibble): 0040
Lane 06 nibble 0 adjusted value (post nibble): 0040
Lane 07 nibble 0 raw readback: 0045
Lane 07 nibble 0 adjusted value (pre nibble): 0045
Lane 07 nibble 0 adjusted value (post nibble): 0045
Lane 08 nibble 0 raw readback: 003d
Lane 08 nibble 0 adjusted value (pre nibble): 003d
Lane 08 nibble 0 adjusted value (post nibble): 003d
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 2: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00393c39 20112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 2 DCT 0
phyAssistedMemFnceTraining: done training node 2 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 005f
Lane 00 new seed: 005f
Lane 01 scaled delay: 0057
Lane 01 new seed: 0057
Lane 02 scaled delay: 0053
Lane 02 new seed: 0053
Lane 03 scaled delay: 0051
Lane 03 new seed: 0051
Lane 04 scaled delay: 0042
Lane 04 new seed: 0042
Lane 05 scaled delay: 0049
Lane 05 new seed: 0049
Lane 06 scaled delay: 004a
Lane 06 new seed: 004a
Lane 07 scaled delay: 0051
Lane 07 new seed: 0051
Lane 08 scaled delay: 0046
Lane 08 new seed: 0046
Lane 00 nibble 0 raw readback: 0061
Lane 00 nibble 0 adjusted value (pre nibble): 0061
Lane 00 nibble 0 adjusted value (post nibble): 0061
Lane 01 nibble 0 raw readback: 0059
Lane 01 nibble 0 adjusted value (pre nibble): 0059
Lane 01 nibble 0 adjusted value (post nibble): 0059
Lane 02 nibble 0 raw readback: 0054
Lane 02 nibble 0 adjusted value (pre nibble): 0054
Lane 02 nibble 0 adjusted value (post nibble): 0054
Lane 03 nibble 0 raw readback: 0051
Lane 03 nibble 0 adjusted value (pre nibble): 0051
Lane 03 nibble 0 adjusted value (post nibble): 0051
Lane 04 nibble 0 raw readback: 0043
Lane 04 nibble 0 adjusted value (pre nibble): 0043
Lane 04 nibble 0 adjusted value (post nibble): 0043
Lane 05 nibble 0 raw readback: 0049
Lane 05 nibble 0 adjusted value (pre nibble): 0049
Lane 05 nibble 0 adjusted value (post nibble): 0049
Lane 06 nibble 0 raw readback: 004d
Lane 06 nibble 0 adjusted value (pre nibble): 004d
Lane 06 nibble 0 adjusted value (post nibble): 004d
Lane 07 nibble 0 raw readback: 0051
Lane 07 nibble 0 adjusted value (pre nibble): 0051
Lane 07 nibble 0 adjusted value (post nibble): 0051
Lane 08 nibble 0 raw readback: 0047
Lane 08 nibble 0 adjusted value (pre nibble): 0047
Lane 08 nibble 0 adjusted value (post nibble): 0047
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 2: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00373a37 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 2 DCT 0
phyAssistedMemFnceTraining: done training node 2 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 0071
Lane 00 new seed: 0071
Lane 01 scaled delay: 0067
Lane 01 new seed: 0067
Lane 02 scaled delay: 0061
Lane 02 new seed: 0061
Lane 03 scaled delay: 005d
Lane 03 new seed: 005d
Lane 04 scaled delay: 004b
Lane 04 new seed: 004b
Lane 05 scaled delay: 0053
Lane 05 new seed: 0053
Lane 06 scaled delay: 0058
Lane 06 new seed: 0058
Lane 07 scaled delay: 005d
Lane 07 new seed: 005d
Lane 08 scaled delay: 0050
Lane 08 new seed: 0050
Lane 00 nibble 0 raw readback: 0030
Lane 00 nibble 0 adjusted value (pre nibble): 0070
Lane 00 nibble 0 adjusted value (post nibble): 0070
Lane 01 nibble 0 raw readback: 0026
Lane 01 nibble 0 adjusted value (pre nibble): 0066
Lane 01 nibble 0 adjusted value (post nibble): 0066
Lane 02 nibble 0 raw readback: 0020
Lane 02 nibble 0 adjusted value (pre nibble): 0060
Lane 02 nibble 0 adjusted value (post nibble): 0060
Lane 03 nibble 0 raw readback: 005d
Lane 03 nibble 0 adjusted value (pre nibble): 005d
Lane 03 nibble 0 adjusted value (post nibble): 005d
Lane 04 nibble 0 raw readback: 004b
Lane 04 nibble 0 adjusted value (pre nibble): 004b
Lane 04 nibble 0 adjusted value (post nibble): 004b
Lane 05 nibble 0 raw readback: 0052
Lane 05 nibble 0 adjusted value (pre nibble): 0052
Lane 05 nibble 0 adjusted value (post nibble): 0052
Lane 06 nibble 0 raw readback: 0056
Lane 06 nibble 0 adjusted value (pre nibble): 0056
Lane 06 nibble 0 adjusted value (post nibble): 0056
Lane 07 nibble 0 raw readback: 005d
Lane 07 nibble 0 adjusted value (pre nibble): 005d
Lane 07 nibble 0 adjusted value (post nibble): 005d
Lane 08 nibble 0 raw readback: 004f
Lane 08 nibble 0 adjusted value (pre nibble): 004f
Lane 08 nibble 0 adjusted value (post nibble): 004f
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
DIMM 1 RttWr: 2
SetTargetFreq: Start
SetTargetFreq: Node 2: New frequency code: 0012
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00363936 30112222
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: training node 2 DCT 0
phyAssistedMemFnceTraining: done training node 2 DCT 0
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00
fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0
mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 3
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 3
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
DIMM 1 RttNom: 3
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
DIMM 1 RttWr: 0
DIMM 1 RttNom: 3
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
DIMM 1 RttWr: 0
Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data
Lane 00 scaled delay: 007f
Lane 00 new seed: 007f
Lane 01 scaled delay: 0073
Lane 01 new seed: 0073
Lane 02 scaled delay: 006c
Lane 02 new seed: 006c
Lane 03 scaled delay: 0069
Lane 03 new seed: 0069
Lane 04 scaled delay: 0053
Lane 04 new seed: 0053
Lane 05 scaled delay: 005b
Lane 05 new seed: 005b
Lane 06 scaled delay: 0060
Lane 06 new seed: 0060
Lane 07 scaled delay: 0069
Lane 07 new seed: 0069
Lane 08 scaled delay: 0058
Lane 08 new seed: 0058
Lane 00 nibble 0 raw readback: 0042
Lane 00 nibble 0 adjusted value (pre nibble): 0082
Lane 00 nibble 0 adjusted value (post nibble): 0082
Lane 01 nibble 0 raw readback: 0036
Lane 01 nibble 0 adjusted value (pre nibble): 0076
Lane 01 nibble 0 adjusted value (post nibble): 0076
Lane 02 nibble 0 raw readback: 0030
Lane 02 nibble 0 adjusted value (pre nibble): 0070
Lane 02 nibble 0 adjusted value (post nibble): 0070
Lane 03 nibble 0 raw readback: 002c
Lane 03 nibble 0 adjusted value (pre nibble): 006c
Lane 03 nibble 0 adjusted value (post nibble): 006c
Lane 04 nibble 0 raw readback: 0056
Lane 04 nibble 0 adjusted value (pre nibble): 0056
Lane 04 nibble 0 adjusted value (post nibble): 0056
Lane 05 nibble 0 raw readback: 005f
Lane 05 nibble 0 adjusted value (pre nibble): 005f
Lane 05 nibble 0 adjusted value (post nibble): 005f
Lane 06 nibble 0 raw readback: 0024
Lane 06 nibble 0 adjusted value (pre nibble): 0064
Lane 06 nibble 0 adjusted value (post nibble): 0064
Lane 07 nibble 0 raw readback: 002c
Lane 07 nibble 0 adjusted value (pre nibble): 006c
Lane 07 nibble 0 adjusted value (post nibble): 006c
Lane 08 nibble 0 raw readback: 005b
Lane 08 nibble 0 adjusted value (pre nibble): 005b
Lane 08 nibble 0 adjusted value (post nibble): 005b
original critical gross delay: 0
new critical gross delay: 0
DIMM 1 RttNom: 3
Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098
DIMM 1 RttWr: 0
DIMM 1 RttNom: 3
Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
DIMM 1 RttNom: 3
DIMM 1 RttWr: 0
Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098
DIMM 1 RttWr: 0
activate_spd_rom() for node 03
enable_spd_node3()
fam15_receiver_enable_training_seed: using seed: 004d
fam15_receiver_enable_training_seed: using seed: 004d
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
fam15_receiver_enable_training_seed: using seed: 0054
fam15_receiver_enable_training_seed: using seed: 0054
TrainRcvrEn: Status 2005
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 4000
TrainDQSReceiverEnCyc: ErrStatus 4000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done
TrainDQSReceiverEnCyc: Status 2005
TrainDQSReceiverEnCyc: TrainErrors 4000
TrainDQSReceiverEnCyc: ErrStatus 4000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done
TrainMaxRdLatency: Status 2205
TrainMaxRdLatency: ErrStatus 4000
TrainMaxRdLatency: ErrCode 0
TrainMaxRdLatency: Done
TrainMaxRdLatency: Status 2005
TrainMaxRdLatency: ErrStatus 4000
TrainMaxRdLatency: ErrCode 0
TrainMaxRdLatency: Done
mctAutoInitMCT_D: :OtherTiming
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
InterleaveNodes_D: Status 2205
InterleaveNodes_D: ErrStatus 4000
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 2205
InterleaveChannels_D: ErrStatus 4000
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 1
InterleaveChannels_D: ErrCode 2
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 2005
InterleaveChannels_D: ErrStatus 4000
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 1
InterleaveChannels_D: ErrCode 2
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
ECC enabled on node: 00
DCTMemClr_Sync_D: Start
DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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.
DCTMemClr_Sync_D: Done
ECC enabled on node: 02
DCTMemClr_Sync_D: Start
DCTMemClr_Sync_D: Waiting for memory clear to complete........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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.
DCTMemClr_Sync_D: Done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
ECCInit: Node 00
ECCInit: Status 2205
ECCInit: ErrStatus 4000
ECCInit: ErrCode 0
ECCInit: Done
ECCInit: Node 01
ECCInit: Status 2000
ECCInit: ErrStatus 1
ECCInit: ErrCode 2
ECCInit: Done
ECCInit: Node 02
ECCInit: Status 2005
ECCInit: ErrStatus 4000
ECCInit: ErrCode 0
ECCInit: Done
ECCInit: Node 03
ECCInit: Status 2000
ECCInit: ErrStatus 1
ECCInit: ErrCode 2
ECCInit: Done
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:c00000
CPUMemTyping: Bottom32bIO:c00000
CPUMemTyping: Bottom40bIO:8400000
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
mctAutoInitMCT_D Done: Global Status: 12
raminit_amdmct end:
Timestamp - after ram initialization: 50956118092
CBMEM:
IMD: root @ bffff000 254 entries.
IMD: root @ bfffec00 62 entries.
Timestamp - start of romstage: 1703750
Timestamp - before ram initialization: 5273866269
Timestamp - after ram initialization: 50830240053
amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
disable_spd()
Timestamp - end of romstage: 51426357718
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 3fe00 size 15f53
Timestamp - starting to load ramstage: 51488376452
Timestamp - starting LZMA decompress (ignore for x86): 51503624837
Timestamp - finished LZMA decompress (ignore for x86): 51709028342
Timestamp - finished loading ramstage: 51728789353
coreboot-4.8.1-6794ce02d45273427c1c6675950c8468380c040a Fri May 18 18:53:13 UTC 2018 ramstage starting...
Moving GDT to bfffe9e0...ok
Timestamp - start of ramstage: 51779217019
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
Timestamp - device enumeration: 51806056128
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3134 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:00.2: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:0c.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:2f: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.106: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 0
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.108: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 0
PNP: 002e.f: enabled 0
PNP: 004e.0: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:19.1: enabled 1
PCI: 00:19.2: enabled 1
PCI: 00:19.3: enabled 1
PCI: 00:19.4: enabled 1
PCI: 00:19.5: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1a.1: enabled 1
PCI: 00:1a.2: enabled 1
PCI: 00:1a.3: enabled 1
PCI: 00:1a.4: enabled 1
PCI: 00:1a.5: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1b.1: enabled 1
PCI: 00:1b.2: enabled 1
PCI: 00:1b.3: enabled 1
PCI: 00:1b.4: enabled 1
PCI: 00:1b.5: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:00.2: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:0c.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:2f: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.106: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 0
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.108: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 0
PNP: 002e.f: enabled 0
PNP: 004e.0: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:19.1: enabled 1
PCI: 00:19.2: enabled 1
PCI: 00:19.3: enabled 1
PCI: 00:19.4: enabled 1
PCI: 00:19.5: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1a.1: enabled 1
PCI: 00:1a.2: enabled 1
PCI: 00:1a.3: enabled 1
PCI: 00:1a.4: enabled 1
PCI: 00:1a.5: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1b.1: enabled 1
PCI: 00:1b.2: enabled 1
PCI: 00:1b.3: enabled 1
PCI: 00:1b.4: enabled 1
PCI: 00:1b.5: enabled 1
Mainboard KGPE-D16 Enable. dev=0x0012e6a0
mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000008
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000008
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
PCI: 00:18.5 siblings=7
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
CPU: APIC: 03 enabled
CPU: APIC: 04 enabled
CPU: APIC: 05 enabled
CPU: APIC: 06 enabled
CPU: APIC: 07 enabled
PCI: 00:19.5 siblings=7
CPU: APIC: 08 enabled
CPU: APIC: 09 enabled
CPU: APIC: 0a enabled
CPU: APIC: 0b enabled
CPU: APIC: 0c enabled
CPU: APIC: 0d enabled
CPU: APIC: 0e enabled
CPU: APIC: 0f enabled
PCI: 00:1a.5 siblings=7
CPU: APIC: 20 enabled
CPU: APIC: 21 enabled
CPU: APIC: 22 enabled
CPU: APIC: 23 enabled
CPU: APIC: 24 enabled
CPU: APIC: 25 enabled
CPU: APIC: 26 enabled
CPU: APIC: 27 enabled
PCI: 00:1b.5 siblings=7
CPU: APIC: 28 enabled
CPU: APIC: 29 enabled
CPU: APIC: 2a enabled
CPU: APIC: 2b enabled
CPU: APIC: 2c enabled
CPU: APIC: 2d enabled
CPU: APIC: 2e enabled
CPU: APIC: 2f enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 80268 usecs
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1600] bus ops
PCI: 00:18.0 [1022/1600] enabled
PCI: 00:18.1 [1022/1601] enabled
PCI: 00:18.2 [1022/1602] enabled
PCI: 00:18.3 [1022/1603] ops
PCI: 00:18.3 [1022/1603] enabled
PCI: 00:18.4 [1022/1604] ops
PCI: 00:18.4 [1022/1604] enabled
PCI: 00:18.5 [1022/1605] ops
PCI: 00:18.5 [1022/1605] enabled
PCI: 00:19.0 [1022/1600] bus ops
PCI: 00:19.0 [1022/1600] enabled
PCI: 00:19.1 [1022/1601] enabled
PCI: 00:19.2 [1022/1602] enabled
PCI: 00:19.3 [1022/1603] ops
PCI: 00:19.3 [1022/1603] enabled
PCI: 00:19.4 [1022/1604] ops
PCI: 00:19.4 [1022/1604] enabled
PCI: 00:19.5 [1022/1605] ops
PCI: 00:19.5 [1022/1605] enabled
PCI: 00:1a.0 [1022/1600] bus ops
PCI: 00:1a.0 [1022/1600] enabled
PCI: 00:1a.1 [1022/1601] enabled
PCI: 00:1a.2 [1022/1602] enabled
PCI: 00:1a.3 [1022/1603] ops
PCI: 00:1a.3 [1022/1603] enabled
PCI: 00:1a.4 [1022/1604] ops
PCI: 00:1a.4 [1022/1604] enabled
PCI: 00:1a.5 [1022/1605] ops
PCI: 00:1a.5 [1022/1605] enabled
PCI: 00:1b.0 [1022/1600] bus ops
PCI: 00:1b.0 [1022/1600] enabled
PCI: 00:1b.1 [1022/1601] enabled
PCI: 00:1b.2 [1022/1602] enabled
PCI: 00:1b.3 [1022/1603] ops
PCI: 00:1b.3 [1022/1603] enabled
PCI: 00:1b.4 [1022/1604] ops
PCI: 00:1b.4 [1022/1604] enabled
PCI: 00:1b.5 [1022/1605] ops
PCI: 00:1b.5 [1022/1605] enabled
PCI: 00:18.0 scanning...
do_hypertransport_scan_chain for bus 00
sr5650_enable: dev=00130fc0, VID_DID=0x5a101002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130a20, port=0x8
PciePowerOffGppPorts() port 8
NB_PCI_REG04 = 2.
NB_PCI_REG84 = 3000010.
NB_PCI_REG4C = 52042.
Sysmem TOM = 0_c0000000
Sysmem TOM2 = 8_40000000
PCI: 00:00.0 [1002/5a10] ops
PCI: 00:00.0 [1002/5a10] enabled
Capability: type 0x08 @ 0xf0
flags: 0xa803
Capability: type 0x08 @ 0xf0
Capability: type 0x08 @ 0xc4
flags: 0x0280
PCI: 00:00.0 count: 0014 static_count: 0015
PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
sr5650_enable: dev=00130fc0, VID_DID=0x5a101002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130a20, port=0x8
PciePowerOffGppPorts() port 8
NB_PCI_REG04 = 2.
NB_PCI_REG84 = 3000010.
NB_PCI_REG4C = 52042.
Sysmem TOM = 0_c0000000
Sysmem TOM2 = 8_40000000
PCI: 00:00.0 [1002/5a10] enabled
sr5650_enable: dev=00130f20, VID_DID=0xffffffff
Bus-0, Dev-0, Fun-1.
PCI: Static device PCI: 00:00.1 not found, disabling it.
sr5650_enable: dev=00130e80, VID_DID=0x5a231002
Bus-0, Dev-0, Fun-2.
PCI: 00:00.2 [1002/5a23] ops
PCI: 00:00.2 [1002/5a23] enabled
sr5650_enable: dev=00130de0, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130de0, port=0x2
PcieLinkTraining port=2:lc current state=2030400
sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0
PciePowerOffGppPorts() port 2
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:02.0 subordinate bus PCI Express
PCI: 00:02.0 [1002/5a16] enabled
sr5650_enable: dev=00130d40, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
sr5650_enable: dev=00130ca0, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130ca0, port=0x4
PcieLinkTraining port=4:lc current state=2030400
sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
PciePowerOffGppPorts() port 4
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1002/5a18] enabled
sr5650_enable: dev=00130c00, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
sr5650_enable: dev=00130b60, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
sr5650_enable: dev=00130ac0, VID_DID=0xffffffff
enable_pcie_bar3
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
sr5650_enable: dev=00130a20, VID_DID=0xffffffff
Bus-0, Dev-8, Fun-0. enable=0
disable_pcie_bar3
sr5650_enable: dev=00130980, VID_DID=0xffffffff
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130980, port=0x9
PcieLinkTraining port=5:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=48
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1002/5a1c] enabled
sr5650_enable: dev=001308e0, VID_DID=0xffffffff
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x001308e0, port=0xa
PcieLinkTraining port=6:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1002/5a1d] enabled
sr5650_enable: dev=00130840, VID_DID=0xffffffff
Bus-0, Dev-11,12, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130840, port=0xb
PcieLinkTraining port=b:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=58
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0xb hw_port=0xb result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0b.0 subordinate bus PCI Express
PCI: 00:0b.0 [1002/5a1f] enabled
sr5650_enable: dev=001307a0, VID_DID=0xffffffff
Bus-0, Dev-11,12, Fun-0. enable=1
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x001307a0, port=0xc
PcieLinkTraining port=c:lc current state=2030400
sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0
PciePowerOffGppPorts() port 12
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0c.0 subordinate bus PCI Express
PCI: 00:0c.0 [1002/5a20] enabled
sr5650_enable: dev=00130700, VID_DID=0xffffffff
sr5650_gpp_sb_init: nb_dev=0x00130fc0, dev=0x00130700, port=0xd
PcieLinkTraining port=d:lc current state=a0b0f10
addr=c0000000,bus=0,devfn=68
PcieTrainPort reg=0x10000
sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0d.0 subordinate bus PCI Express
PCI: 00:0d.0 [1002/5a1e] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4394] ops
PCI: 00:11.0 [1002/4394] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:02.0 scanning...
do_pci_scan_bridge for PCI: 00:02.0
PCI: pci_scan_bus for bus 01
scan_bus: scanning of bus PCI: 00:02.0 took 6512 usecs
PCI: 00:04.0 scanning...
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:04.0 took 6513 usecs
PCI: 00:09.0 scanning...
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [8086/10d3] enabled
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Failed to enable LTR for dev = PCI: 03:00.0
scan_bus: scanning of bus PCI: 00:09.0 took 35762 usecs
PCI: 00:0a.0 scanning...
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [8086/10d3] enabled
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Failed to enable LTR for dev = PCI: 04:00.0
scan_bus: scanning of bus PCI: 00:0a.0 took 35755 usecs
PCI: 00:0b.0 scanning...
do_pci_scan_bridge for PCI: 00:0b.0
PCI: pci_scan_bus for bus 05
PCI: 05:00.0 [1002/67ef] enabled
PCI: 05:00.1 [1002/aae0] enabled
Capability: type 0x09 @ 0x48
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
Capability: type 0x09 @ 0x48
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
Capability: type 0x09 @ 0x48
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x09 @ 0x48
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
scan_bus: scanning of bus PCI: 00:0b.0 took 58483 usecs
PCI: 00:0c.0 scanning...
do_pci_scan_bridge for PCI: 00:0c.0
PCI: pci_scan_bus for bus 06
scan_bus: scanning of bus PCI: 00:0c.0 took 6513 usecs
PCI: 00:0d.0 scanning...
do_pci_scan_bridge for PCI: 00:0d.0
PCI: pci_scan_bus for bus 07
PCI: 07:00.0 [168c/0030] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Failed to enable LTR for dev = PCI: 07:00.0
scan_bus: scanning of bus PCI: 00:0d.0 took 35756 usecs
PCI: 00:14.0 scanning...
scan_generic_bus for PCI: 00:14.0
bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
bus: PCI: 00:14.0[0]->I2C: 01:54 enabled
bus: PCI: 00:14.0[0]->I2C: 01:55 enabled
bus: PCI: 00:14.0[0]->I2C: 01:56 enabled
bus: PCI: 00:14.0[0]->I2C: 01:57 enabled
bus: PCI: 00:14.0[0]->I2C: 01:2f enabled
scan_generic_bus for PCI: 00:14.0 done
scan_bus: scanning of bus PCI: 00:14.0 took 33502 usecs
PCI: 00:14.3 scanning...
scan_lpc_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.106 disabled
PNP: 002e.107 disabled
PNP: 002e.207 disabled
PNP: 002e.307 disabled
PNP: 002e.407 disabled
PNP: 002e.8 disabled
PNP: 002e.108 disabled
PNP: 002e.9 disabled
PNP: 002e.109 disabled
PNP: 002e.209 disabled
PNP: 002e.309 disabled
PNP: 002e.a enabled
PNP: 002e.b enabled
PNP: 002e.c disabled
PNP: 002e.d disabled
PNP: 002e.f disabled
PNP: 004e.0 enabled
scan_lpc_bus for PCI: 00:14.3 done
scan_bus: scanning of bus PCI: 00:14.3 took 41433 usecs
PCI: 00:14.4 scanning...
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 08
sb7xx_51xx_enable()
PCI: Static device PCI: 08:01.0 not found, disabling it.
sb7xx_51xx_enable()
PCI: Static device PCI: 08:02.0 not found, disabling it.
sb7xx_51xx_enable()
PCI: 08:03.0 [1102/0002] enabled
PCI: 08:03.1 [1102/7002] enabled
scan_bus: scanning of bus PCI: 00:14.4 took 23761 usecs
scan_bus: scanning of bus PCI: 00:18.0 took 1990163 usecs
PCI: 00:19.0 scanning...
scan_bus: scanning of bus PCI: 00:19.0 took 1817 usecs
PCI: 00:1a.0 scanning...
scan_bus: scanning of bus PCI: 00:1a.0 took 1817 usecs
PCI: 00:1b.0 scanning...
scan_bus: scanning of bus PCI: 00:1b.0 took 1817 usecs
DOMAIN: 0000 passpw: enabled
DOMAIN: 0000 passpw: enabled
DOMAIN: 0000 passpw: enabled
DOMAIN: 0000 passpw: enabled
scan_bus: scanning of bus DOMAIN: 0000 took 2115401 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 2223816 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 2577350 exit 0
Timestamp - device configuration: 60867022135
found VGA at PCI: 05:00.0
Setting up VGA for PCI: 05:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0b.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
sr5690_read_resource: PCI: 00:00.0
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
PCI: 00:02.0 read_resources bus 1 link: 0
PCI: 00:02.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 2 link: 0
PCI: 00:04.0 read_resources bus 2 link: 0 done
PCI: 00:09.0 read_resources bus 3 link: 0
PCI: 00:09.0 read_resources bus 3 link: 0 done
PCI: 00:0a.0 read_resources bus 4 link: 0
PCI: 00:0a.0 read_resources bus 4 link: 0 done
PCI: 00:0b.0 read_resources bus 5 link: 0
PCI: 00:0b.0 read_resources bus 5 link: 0 done
PCI: 00:0c.0 read_resources bus 6 link: 0
PCI: 00:0c.0 read_resources bus 6 link: 0 done
PCI: 00:0d.0 read_resources bus 7 link: 0
PCI: 00:0d.0 read_resources bus 7 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
I2C: 01:54 missing read_resources
I2C: 01:55 missing read_resources
I2C: 01:56 missing read_resources
I2C: 01:57 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PNP: 004e.0 missing read_resources
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 8 link: 0
PCI: 00:14.4 read_resources bus 8 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1 done
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
PCI: 00:18.4 read_resources bus 0 link: 0
PCI: 00:18.4 read_resources bus 0 link: 0 done
PCI: 00:18.4 read_resources bus 0 link: 1
PCI: 00:18.4 read_resources bus 0 link: 1 done
PCI: 00:18.4 read_resources bus 0 link: 2
PCI: 00:18.4 read_resources bus 0 link: 2 done
PCI: 00:18.4 read_resources bus 0 link: 3
PCI: 00:18.4 read_resources bus 0 link: 3 done
PCI: 00:19.0 read_resources bus 0 link: 3
PCI: 00:19.0 read_resources bus 0 link: 3 done
PCI: 00:19.0 read_resources bus 0 link: 2
PCI: 00:19.0 read_resources bus 0 link: 2 done
PCI: 00:19.0 read_resources bus 0 link: 0
PCI: 00:19.0 read_resources bus 0 link: 0 done
PCI: 00:19.0 read_resources bus 0 link: 1
PCI: 00:19.0 read_resources bus 0 link: 1 done
PCI: 00:19.4 read_resources bus 0 link: 0
PCI: 00:19.4 read_resources bus 0 link: 0 done
PCI: 00:19.4 read_resources bus 0 link: 1
PCI: 00:19.4 read_resources bus 0 link: 1 done
PCI: 00:19.4 read_resources bus 0 link: 2
PCI: 00:19.4 read_resources bus 0 link: 2 done
PCI: 00:19.4 read_resources bus 0 link: 3
PCI: 00:19.4 read_resources bus 0 link: 3 done
PCI: 00:1a.0 read_resources bus 0 link: 3
PCI: 00:1a.0 read_resources bus 0 link: 3 done
PCI: 00:1a.0 read_resources bus 0 link: 2
PCI: 00:1a.0 read_resources bus 0 link: 2 done
PCI: 00:1a.0 read_resources bus 0 link: 0
PCI: 00:1a.0 read_resources bus 0 link: 0 done
PCI: 00:1a.0 read_resources bus 0 link: 1
PCI: 00:1a.0 read_resources bus 0 link: 1 done
PCI: 00:1a.4 read_resources bus 0 link: 0
PCI: 00:1a.4 read_resources bus 0 link: 0 done
PCI: 00:1a.4 read_resources bus 0 link: 1
PCI: 00:1a.4 read_resources bus 0 link: 1 done
PCI: 00:1a.4 read_resources bus 0 link: 2
PCI: 00:1a.4 read_resources bus 0 link: 2 done
PCI: 00:1a.4 read_resources bus 0 link: 3
PCI: 00:1a.4 read_resources bus 0 link: 3 done
PCI: 00:1b.0 read_resources bus 0 link: 3
PCI: 00:1b.0 read_resources bus 0 link: 3 done
PCI: 00:1b.0 read_resources bus 0 link: 2
PCI: 00:1b.0 read_resources bus 0 link: 2 done
PCI: 00:1b.0 read_resources bus 0 link: 0
PCI: 00:1b.0 read_resources bus 0 link: 0 done
PCI: 00:1b.0 read_resources bus 0 link: 1
PCI: 00:1b.0 read_resources bus 0 link: 1 done
PCI: 00:1b.4 read_resources bus 0 link: 0
PCI: 00:1b.4 read_resources bus 0 link: 0 done
PCI: 00:1b.4 read_resources bus 0 link: 1
PCI: 00:1b.4 read_resources bus 0 link: 1 done
PCI: 00:1b.4 read_resources bus 0 link: 2
PCI: 00:1b.4 read_resources bus 0 link: 2 done
PCI: 00:1b.4 read_resources bus 0 link: 3
PCI: 00:1b.4 read_resources bus 0 link: 3 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
APIC: 02
APIC: 03
APIC: 04
APIC: 05
APIC: 06
APIC: 07
APIC: 08
APIC: 09
APIC: 0a
APIC: 0b
APIC: 0c
APIC: 0d
APIC: 0e
APIC: 0f
APIC: 20
APIC: 21
APIC: 22
APIC: 23
APIC: 24
APIC: 25
APIC: 26
APIC: 27
APIC: 28
APIC: 29
APIC: 2a
APIC: 2b
APIC: 2c
APIC: 2d
APIC: 2e
APIC: 2f
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
PCI: 00:18.0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
PCI: 00:00.1
PCI: 00:00.2
PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0 child on link 0 PCI: 03:00.0
PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:0b.0 child on link 0 PCI: 05:00.0
PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 05:00.0
PCI: 05:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 10
PCI: 05:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 18
PCI: 05:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20
PCI: 05:00.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24
PCI: 05:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 05:00.1
PCI: 05:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:0c.0
PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:0d.0 child on link 0 PCI: 07:00.0
PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 07:00.0
PCI: 07:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
PCI: 07:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:2f
PCI: 00:14.1
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 002e.106
PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
PNP: 002e.107
PNP: 002e.207
PNP: 002e.307
PNP: 002e.407
PNP: 002e.8
PNP: 002e.108
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.d
PNP: 002e.f
PNP: 004e.0
PCI: 00:14.4 child on link 0 PCI: 08:01.0
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 08:01.0
PCI: 08:02.0
PCI: 08:03.0
PCI: 08:03.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10
PCI: 08:03.1
PCI: 08:03.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:19.0
PCI: 00:19.1
PCI: 00:19.2
PCI: 00:19.3
PCI: 00:19.4
PCI: 00:19.5
PCI: 00:1a.0
PCI: 00:1a.1
PCI: 00:1a.2
PCI: 00:1a.3
PCI: 00:1a.4
PCI: 00:1a.5
PCI: 00:1b.0
PCI: 00:1b.1
PCI: 00:1b.2
PCI: 00:1b.3
PCI: 00:1b.4
PCI: 00:1b.5
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 18 * [0x0 - 0x1f] io
PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 04:00.0 18 * [0x0 - 0x1f] io
PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 05:00.0 20 * [0x0 - 0xff] io
PCI: 00:0b.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 08:03.0 10 * [0x0 - 0x1f] io
PCI: 08:03.1 10 * [0x20 - 0x27] io
PCI: 00:14.4 io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:09.0 1c * [0x0 - 0xfff] io
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
PCI: 00:0b.0 1c * [0x2000 - 0x2fff] io
PCI: 00:14.4 1c * [0x3000 - 0x3fff] io
PCI: 00:11.0 20 * [0x4000 - 0x400f] io
PCI: 00:14.1 20 * [0x4010 - 0x401f] io
PCI: 00:11.0 10 * [0x4020 - 0x4027] io
PCI: 00:11.0 18 * [0x4028 - 0x402f] io
PCI: 00:14.1 10 * [0x4030 - 0x4037] io
PCI: 00:14.1 18 * [0x4038 - 0x403f] io
PCI: 00:11.0 14 * [0x4040 - 0x4043] io
PCI: 00:11.0 1c * [0x4044 - 0x4047] io
PCI: 00:14.1 14 * [0x4048 - 0x404b] io
PCI: 00:14.1 1c * [0x404c - 0x404f] io
PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 110d8 * [0x0 - 0x4fff] io
DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 05:00.0 10 * [0x0 - 0xfffffff] prefmem
PCI: 05:00.0 18 * [0x10000000 - 0x101fffff] prefmem
PCI: 00:0b.0 prefmem: base: 10200000 size: 10200000 align: 28 gran: 20 limit: ffffffffffffffff done
PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0b.0 24 * [0x0 - 0x101fffff] prefmem
PCI: 00:00.0 fc * [0x10200000 - 0x102000ff] prefmem
PCI: 00:18.0 prefmem: base: 10200100 size: 10300000 align: 28 gran: 20 limit: ffffffff done
PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 05:00.0 24 * [0x0 - 0x3ffff] mem
PCI: 05:00.0 30 * [0x40000 - 0x5ffff] mem
PCI: 05:00.1 10 * [0x60000 - 0x63fff] mem
PCI: 00:0b.0 mem: base: 64000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 07:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 07:00.0 30 * [0x20000 - 0x2ffff] mem
PCI: 00:0d.0 mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:09.0 20 * [0x0 - 0xfffff] mem
PCI: 00:0a.0 20 * [0x100000 - 0x1fffff] mem
PCI: 00:0b.0 20 * [0x200000 - 0x2fffff] mem
PCI: 00:0d.0 20 * [0x300000 - 0x3fffff] mem
PCI: 00:00.2 44 * [0x400000 - 0x403fff] mem
PCI: 00:14.2 10 * [0x404000 - 0x407fff] mem
PCI: 00:12.0 10 * [0x408000 - 0x408fff] mem
PCI: 00:12.1 10 * [0x409000 - 0x409fff] mem
PCI: 00:13.0 10 * [0x40a000 - 0x40afff] mem
PCI: 00:13.1 10 * [0x40b000 - 0x40bfff] mem
PCI: 00:14.5 10 * [0x40c000 - 0x40cfff] mem
PCI: 00:11.0 24 * [0x40d000 - 0x40d3ff] mem
PCI: 00:12.2 10 * [0x40e000 - 0x40e0ff] mem
PCI: 00:13.2 10 * [0x40f000 - 0x40f0ff] mem
PCI: 00:14.3 a0 * [0x410000 - 0x410000] mem
PCI: 00:18.0 mem: base: 410001 size: 500000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.0 110b0 * [0x0 - 0x102fffff] prefmem
PCI: 00:18.3 94 * [0x14000000 - 0x17ffffff] mem
PCI: 00:18.0 110b8 * [0x18000000 - 0x184fffff] mem
DOMAIN: 0000 mem: base: 18500000 size: 18500000 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
constrain_resources: PCI: 00:14.0 9c base feb00000 limit feb00fff mem (fixed)
constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit feafffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
PCI: 00:18.0 110d8 * [0x1000 - 0x5fff] io
DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
PCI: 00:09.0 1c * [0x1000 - 0x1fff] io
PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
PCI: 00:0b.0 1c * [0x3000 - 0x3fff] io
PCI: 00:14.4 1c * [0x4000 - 0x4fff] io
PCI: 00:11.0 20 * [0x5000 - 0x500f] io
PCI: 00:14.1 20 * [0x5010 - 0x501f] io
PCI: 00:11.0 10 * [0x5020 - 0x5027] io
PCI: 00:11.0 18 * [0x5028 - 0x502f] io
PCI: 00:14.1 10 * [0x5030 - 0x5037] io
PCI: 00:14.1 18 * [0x5038 - 0x503f] io
PCI: 00:11.0 14 * [0x5040 - 0x5043] io
PCI: 00:11.0 1c * [0x5044 - 0x5047] io
PCI: 00:14.1 14 * [0x5048 - 0x504b] io
PCI: 00:14.1 1c * [0x504c - 0x504f] io
PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done
PCI: 00:02.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
PCI: 00:02.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
PCI: 03:00.0 18 * [0x1000 - 0x101f] io
PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 04:00.0 18 * [0x2000 - 0x201f] io
PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
PCI: 00:0b.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
PCI: 05:00.0 20 * [0x3000 - 0x30ff] io
PCI: 00:0b.0 io: next_base: 3100 size: 1000 align: 12 gran: 12 done
PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
PCI: 00:0d.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
PCI: 00:0d.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff
PCI: 08:03.0 10 * [0x4000 - 0x401f] io
PCI: 08:03.1 10 * [0x4020 - 0x4027] io
PCI: 00:14.4 io: next_base: 4028 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e0000000 size:18500000 align:28 gran:0 limit:feafffff
PCI: 00:18.0 110b0 * [0xe0000000 - 0xf02fffff] prefmem
PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem
PCI: 00:18.0 110b8 * [0xf8000000 - 0xf84fffff] mem
DOMAIN: 0000 mem: next_base: f8500000 size: 18500000 align: 28 gran: 0 done
PCI: 00:18.0 prefmem: base:e0000000 size:10300000 align:28 gran:20 limit:f02fffff
PCI: 00:0b.0 24 * [0xe0000000 - 0xf01fffff] prefmem
PCI: 00:00.0 fc * [0xf0200000 - 0xf02000ff] prefmem
PCI: 00:18.0 prefmem: next_base: f0200100 size: 10300000 align: 28 gran: 20 done
PCI: 00:02.0 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:02.0 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:04.0 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:04.0 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:09.0 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:0a.0 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:0a.0 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:0b.0 prefmem: base:e0000000 size:10200000 align:28 gran:20 limit:f01fffff
PCI: 05:00.0 10 * [0xe0000000 - 0xefffffff] prefmem
PCI: 05:00.0 18 * [0xf0000000 - 0xf01fffff] prefmem
PCI: 00:0b.0 prefmem: next_base: f0200000 size: 10200000 align: 28 gran: 20 done
PCI: 00:0c.0 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:0c.0 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:0d.0 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:0d.0 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 prefmem: base:f02fffff size:0 align:20 gran:20 limit:f02fffff
PCI: 00:14.4 prefmem: next_base: f02fffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 mem: base:f8000000 size:500000 align:20 gran:20 limit:f84fffff
PCI: 00:09.0 20 * [0xf8000000 - 0xf80fffff] mem
PCI: 00:0a.0 20 * [0xf8100000 - 0xf81fffff] mem
PCI: 00:0b.0 20 * [0xf8200000 - 0xf82fffff] mem
PCI: 00:0d.0 20 * [0xf8300000 - 0xf83fffff] mem
PCI: 00:00.2 44 * [0xf8400000 - 0xf8403fff] mem
PCI: 00:14.2 10 * [0xf8404000 - 0xf8407fff] mem
PCI: 00:12.0 10 * [0xf8408000 - 0xf8408fff] mem
PCI: 00:12.1 10 * [0xf8409000 - 0xf8409fff] mem
PCI: 00:13.0 10 * [0xf840a000 - 0xf840afff] mem
PCI: 00:13.1 10 * [0xf840b000 - 0xf840bfff] mem
PCI: 00:14.5 10 * [0xf840c000 - 0xf840cfff] mem
PCI: 00:11.0 24 * [0xf840d000 - 0xf840d3ff] mem
PCI: 00:12.2 10 * [0xf840e000 - 0xf840e0ff] mem
PCI: 00:13.2 10 * [0xf840f000 - 0xf840f0ff] mem
PCI: 00:14.3 a0 * [0xf8410000 - 0xf8410000] mem
PCI: 00:18.0 mem: next_base: f8410001 size: 500000 align: 20 gran: 20 done
PCI: 00:02.0 mem: base:f84fffff size:0 align:20 gran:20 limit:f84fffff
PCI: 00:02.0 mem: next_base: f84fffff size: 0 align: 20 gran: 20 done
PCI: 00:04.0 mem: base:f84fffff size:0 align:20 gran:20 limit:f84fffff
PCI: 00:04.0 mem: next_base: f84fffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 mem: base:f8000000 size:100000 align:20 gran:20 limit:f80fffff
PCI: 03:00.0 10 * [0xf8000000 - 0xf801ffff] mem
PCI: 03:00.0 1c * [0xf8020000 - 0xf8023fff] mem
PCI: 00:09.0 mem: next_base: f8024000 size: 100000 align: 20 gran: 20 done
PCI: 00:0a.0 mem: base:f8100000 size:100000 align:20 gran:20 limit:f81fffff
PCI: 04:00.0 10 * [0xf8100000 - 0xf811ffff] mem
PCI: 04:00.0 1c * [0xf8120000 - 0xf8123fff] mem
PCI: 00:0a.0 mem: next_base: f8124000 size: 100000 align: 20 gran: 20 done
PCI: 00:0b.0 mem: base:f8200000 size:100000 align:20 gran:20 limit:f82fffff
PCI: 05:00.0 24 * [0xf8200000 - 0xf823ffff] mem
PCI: 05:00.0 30 * [0xf8240000 - 0xf825ffff] mem
PCI: 05:00.1 10 * [0xf8260000 - 0xf8263fff] mem
PCI: 00:0b.0 mem: next_base: f8264000 size: 100000 align: 20 gran: 20 done
PCI: 00:0c.0 mem: base:f84fffff size:0 align:20 gran:20 limit:f84fffff
PCI: 00:0c.0 mem: next_base: f84fffff size: 0 align: 20 gran: 20 done
PCI: 00:0d.0 mem: base:f8300000 size:100000 align:20 gran:20 limit:f83fffff
PCI: 07:00.0 10 * [0xf8300000 - 0xf831ffff] mem
PCI: 07:00.0 30 * [0xf8320000 - 0xf832ffff] mem
PCI: 00:0d.0 mem: next_base: f8330000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 mem: base:f84fffff size:0 align:20 gran:20 limit:f84fffff
PCI: 00:14.4 mem: next_base: f84fffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=00300000, basek=00400000, limitk=01100000
2: mmio_basek=00300000, basek=01100000, limitk=02100000
DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
PCI: 00:18.0 110b0 <- [0x00e0000000 - 0x00f02fffff] size 0x10300000 gran 0x14 prefmem <node 0 link 1>
PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00f84fffff] size 0x00500000 gran 0x14 mem <node 0 link 1>
PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1>
PCI: 00:18.0 assign_resources, bus 0 link: 1
PCI: 00:00.0 sr5690_set_resources
sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig>
sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90
PCI: 00:00.0 fc <- [0x00f0200000 - 0x00f02000ff] size 0x00000100 gran 0x08 prefmem
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
PCI: 00:00.2 44 <- [0x00f8400000 - 0x00f8403fff] size 0x00004000 gran 0x0e mem
PCI: 00:02.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:02.0 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:02.0 20 <- [0x00f84fffff - 0x00f84ffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:04.0 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:04.0 20 <- [0x00f84fffff - 0x00f84ffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:09.0 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:09.0 20 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00f8000000 - 0x00f801ffff] size 0x00020000 gran 0x11 mem
PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 03:00.0 1c <- [0x00f8020000 - 0x00f8023fff] size 0x00004000 gran 0x0e mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:0a.0 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:0a.0 20 <- [0x00f8100000 - 0x00f81fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00f8100000 - 0x00f811ffff] size 0x00020000 gran 0x11 mem
PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 04:00.0 1c <- [0x00f8120000 - 0x00f8123fff] size 0x00004000 gran 0x0e mem
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 00:0b.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 05 io
PCI: 00:0b.0 24 <- [0x00e0000000 - 0x00f01fffff] size 0x10200000 gran 0x14 bus 05 prefmem
PCI: 00:0b.0 20 <- [0x00f8200000 - 0x00f82fffff] size 0x00100000 gran 0x14 bus 05 mem
PCI: 00:0b.0 assign_resources, bus 5 link: 0
PCI: 05:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 05:00.0 18 <- [0x00f0000000 - 0x00f01fffff] size 0x00200000 gran 0x15 prefmem64
PCI: 05:00.0 20 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io
PCI: 05:00.0 24 <- [0x00f8200000 - 0x00f823ffff] size 0x00040000 gran 0x12 mem
PCI: 05:00.0 30 <- [0x00f8240000 - 0x00f825ffff] size 0x00020000 gran 0x11 romem
PCI: 05:00.1 10 <- [0x00f8260000 - 0x00f8263fff] size 0x00004000 gran 0x0e mem64
PCI: 00:0b.0 assign_resources, bus 5 link: 0
PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io
PCI: 00:0c.0 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 06 prefmem
PCI: 00:0c.0 20 <- [0x00f84fffff - 0x00f84ffffe] size 0x00000000 gran 0x14 bus 06 mem
PCI: 00:0d.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 07 io
PCI: 00:0d.0 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 07 prefmem
PCI: 00:0d.0 20 <- [0x00f8300000 - 0x00f83fffff] size 0x00100000 gran 0x14 bus 07 mem
PCI: 00:0d.0 assign_resources, bus 7 link: 0
PCI: 07:00.0 10 <- [0x00f8300000 - 0x00f831ffff] size 0x00020000 gran 0x11 mem64
PCI: 07:00.0 30 <- [0x00f8320000 - 0x00f832ffff] size 0x00010000 gran 0x10 romem
PCI: 00:0d.0 assign_resources, bus 7 link: 0
PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f840d000 - 0x00f840d3ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f8408000 - 0x00f8408fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.1 10 <- [0x00f8409000 - 0x00f8409fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00f840e000 - 0x00f840e0ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f840a000 - 0x00f840afff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00f840b000 - 0x00f840bfff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00f840f000 - 0x00f840f0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00f8404000 - 0x00f8407fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00f8410000 - 0x00f8410000] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io
PCI: 00:14.4 24 <- [0x00f02fffff - 0x00f02ffffe] size 0x00000000 gran 0x14 bus 08 prefmem
PCI: 00:14.4 20 <- [0x00f84fffff - 0x00f84ffffe] size 0x00000000 gran 0x14 bus 08 mem
PCI: 00:14.4 assign_resources, bus 8 link: 0
PCI: 08:03.0 10 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io
PCI: 08:03.1 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io
PCI: 00:14.4 assign_resources, bus 8 link: 0
PCI: 00:14.5 10 <- [0x00f840c000 - 0x00f840cfff] size 0x00001000 gran 0x0c mem
PCI: 00:18.0 assign_resources, bus 0 link: 1
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:19.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:1a.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:1b.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
APIC: 02
APIC: 03
APIC: 04
APIC: 05
APIC: 06
APIC: 07
APIC: 08
APIC: 09
APIC: 0a
APIC: 0b
APIC: 0c
APIC: 0d
APIC: 0e
APIC: 0f
APIC: 20
APIC: 21
APIC: 22
APIC: 23
APIC: 24
APIC: 25
APIC: 26
APIC: 27
APIC: 28
APIC: 29
APIC: 2a
APIC: 2b
APIC: 2c
APIC: 2d
APIC: 2e
APIC: 2f
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base e0000000 size 18500000 align 28 gran 0 limit feafffff flags 40040200 index 10000100
DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
DOMAIN: 0000 resource base 100000000 size 340000000 align 0 gran 0 limit 0 flags e0004200 index 30
DOMAIN: 0000 resource base 440000000 size 400000000 align 0 gran 0 limit 0 flags e0004200 index 42
PCI: 00:18.0
PCI: 00:18.0 resource base e0000000 size 10300000 align 28 gran 20 limit f02fffff flags 60081200 index 110b0
PCI: 00:18.0 resource base f8000000 size 500000 align 20 gran 20 limit f84fffff flags 60080200 index 110b8
PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8
PCI: 00:00.0
PCI: 00:00.0 resource base f0200000 size 100 align 12 gran 8 limit f02000ff flags 60001200 index fc
PCI: 00:00.1
PCI: 00:00.2
PCI: 00:00.2 resource base f8400000 size 4000 align 14 gran 14 limit f8403fff flags 70000200 index 44
PCI: 00:02.0
PCI: 00:02.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
PCI: 00:02.0 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:02.0 resource base f84fffff size 0 align 20 gran 20 limit f84fffff flags 60080202 index 20
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
PCI: 00:04.0 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:04.0 resource base f84fffff size 0 align 20 gran 20 limit f84fffff flags 60080202 index 20
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0 child on link 0 PCI: 03:00.0
PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
PCI: 00:09.0 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:09.0 resource base f8000000 size 100000 align 20 gran 20 limit f80fffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base f8000000 size 20000 align 17 gran 17 limit f801ffff flags 60000200 index 10
PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
PCI: 03:00.0 resource base f8020000 size 4000 align 14 gran 14 limit f8023fff flags 60000200 index 1c
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
PCI: 00:0a.0 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:0a.0 resource base f8100000 size 100000 align 20 gran 20 limit f81fffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base f8100000 size 20000 align 17 gran 17 limit f811ffff flags 60000200 index 10
PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
PCI: 04:00.0 resource base f8120000 size 4000 align 14 gran 14 limit f8123fff flags 60000200 index 1c
PCI: 00:0b.0 child on link 0 PCI: 05:00.0
PCI: 00:0b.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
PCI: 00:0b.0 resource base e0000000 size 10200000 align 28 gran 20 limit f01fffff flags 60081202 index 24
PCI: 00:0b.0 resource base f8200000 size 100000 align 20 gran 20 limit f82fffff flags 60080202 index 20
PCI: 05:00.0
PCI: 05:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 10
PCI: 05:00.0 resource base f0000000 size 200000 align 21 gran 21 limit f01fffff flags 60001201 index 18
PCI: 05:00.0 resource base 3000 size 100 align 8 gran 8 limit 30ff flags 60000100 index 20
PCI: 05:00.0 resource base f8200000 size 40000 align 18 gran 18 limit f823ffff flags 60000200 index 24
PCI: 05:00.0 resource base f8240000 size 20000 align 17 gran 17 limit f825ffff flags 60002200 index 30
PCI: 05:00.1
PCI: 05:00.1 resource base f8260000 size 4000 align 14 gran 14 limit f8263fff flags 60000201 index 10
PCI: 00:0c.0
PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
PCI: 00:0c.0 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:0c.0 resource base f84fffff size 0 align 20 gran 20 limit f84fffff flags 60080202 index 20
PCI: 00:0d.0 child on link 0 PCI: 07:00.0
PCI: 00:0d.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
PCI: 00:0d.0 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:0d.0 resource base f8300000 size 100000 align 20 gran 20 limit f83fffff flags 60080202 index 20
PCI: 07:00.0
PCI: 07:00.0 resource base f8300000 size 20000 align 17 gran 17 limit f831ffff flags 60000201 index 10
PCI: 07:00.0 resource base f8320000 size 10000 align 16 gran 16 limit f832ffff flags 60002200 index 30
PCI: 00:11.0
PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10
PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14
PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18
PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c
PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20
PCI: 00:11.0 resource base f840d000 size 400 align 12 gran 10 limit f840d3ff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base f8408000 size 1000 align 12 gran 12 limit f8408fff flags 60000200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base f8409000 size 1000 align 12 gran 12 limit f8409fff flags 60000200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base f840e000 size 100 align 12 gran 8 limit f840e0ff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base f840a000 size 1000 align 12 gran 12 limit f840afff flags 60000200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base f840b000 size 1000 align 12 gran 12 limit f840bfff flags 60000200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base f840f000 size 100 align 12 gran 8 limit f840f0ff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:2f
PCI: 00:14.1
PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10
PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14
PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18
PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c
PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base f8404000 size 4000 align 14 gran 14 limit f8407fff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base f8410000 size 1 align 12 gran 0 limit f8410000 flags 60000200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 002e.106
PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
PNP: 002e.107
PNP: 002e.207
PNP: 002e.307
PNP: 002e.407
PNP: 002e.8
PNP: 002e.108
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.d
PNP: 002e.f
PNP: 004e.0
PCI: 00:14.4 child on link 0 PCI: 08:01.0
PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
PCI: 00:14.4 resource base f02fffff size 0 align 20 gran 20 limit f02fffff flags 60081202 index 24
PCI: 00:14.4 resource base f84fffff size 0 align 20 gran 20 limit f84fffff flags 60080202 index 20
PCI: 08:01.0
PCI: 08:02.0
PCI: 08:03.0
PCI: 08:03.0 resource base 4000 size 20 align 5 gran 5 limit 401f flags 60000100 index 10
PCI: 08:03.1
PCI: 08:03.1 resource base 4020 size 8 align 3 gran 3 limit 4027 flags 60000100 index 10
PCI: 00:14.5
PCI: 00:14.5 resource base f840c000 size 1000 align 12 gran 12 limit f840cfff flags 60000200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit f7ffffff flags 60000200 index 94
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:19.0
PCI: 00:19.1
PCI: 00:19.2
PCI: 00:19.3
PCI: 00:19.4
PCI: 00:19.5
PCI: 00:1a.0
PCI: 00:1a.1
PCI: 00:1a.2
PCI: 00:1a.3
PCI: 00:1a.4
PCI: 00:1a.5
PCI: 00:1b.0
PCI: 00:1b.1
PCI: 00:1b.2
PCI: 00:1b.3
PCI: 00:1b.4
PCI: 00:1b.5
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 3592619 exit 0
Timestamp - device enable: 73456042560
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1043/8163
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1043/8163
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 cmd <- 00
PCI: 00:19.0 cmd <- 00
PCI: 00:19.1 subsystem <- 1043/8163
PCI: 00:19.1 cmd <- 00
PCI: 00:19.2 subsystem <- 1043/8163
PCI: 00:19.2 cmd <- 00
PCI: 00:19.3 cmd <- 00
PCI: 00:19.4 cmd <- 00
PCI: 00:19.5 cmd <- 00
PCI: 00:1a.0 cmd <- 00
PCI: 00:1a.1 subsystem <- 1043/8163
PCI: 00:1a.1 cmd <- 00
PCI: 00:1a.2 subsystem <- 1043/8163
PCI: 00:1a.2 cmd <- 00
PCI: 00:1a.3 cmd <- 00
PCI: 00:1a.4 cmd <- 00
PCI: 00:1a.5 cmd <- 00
PCI: 00:1b.0 cmd <- 00
PCI: 00:1b.1 subsystem <- 1043/8163
PCI: 00:1b.1 cmd <- 00
PCI: 00:1b.2 subsystem <- 1043/8163
PCI: 00:1b.2 cmd <- 00
PCI: 00:1b.3 cmd <- 00
PCI: 00:1b.4 cmd <- 00
PCI: 00:1b.5 cmd <- 00
PCI: 00:00.0 subsystem <- 1043/8163
PCI: 00:00.0 cmd <- 02
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Initializing IOMMU
PCI: 00:02.0 bridge ctrl <- 0003
PCI: 00:02.0 cmd <- 00
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 00
PCI: 00:09.0 bridge ctrl <- 0003
PCI: 00:09.0 cmd <- 07
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 07
PCI: 00:0b.0 bridge ctrl <- 000b
PCI: 00:0b.0 cmd <- 07
PCI: 00:0c.0 bridge ctrl <- 0003
PCI: 00:0c.0 cmd <- 00
PCI: 00:0d.0 bridge ctrl <- 0003
PCI: 00:0d.0 cmd <- 06
PCI: 00:11.0 subsystem <- 1043/8163
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1043/8163
PCI: 00:12.0 cmd <- 02
PCI: 00:12.1 subsystem <- 1043/8163
PCI: 00:12.1 cmd <- 02
PCI: 00:12.2 subsystem <- 1043/8163
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1043/8163
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1043/8163
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1043/8163
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1043/8163
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1043/8163
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 1043/8163
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1043/8163
PCI: 00:14.3 cmd <- 0f
sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 05
PCI: 00:14.5 subsystem <- 1043/8163
PCI: 00:14.5 cmd <- 02
PCI: 03:00.0 cmd <- 03
PCI: 04:00.0 cmd <- 03
PCI: 05:00.0 cmd <- 03
PCI: 05:00.1 cmd <- 02
PCI: 07:00.0 cmd <- 02
PCI: 08:03.0 subsystem <- 1043/8163
PCI: 08:03.0 cmd <- 01
PCI: 08:03.1 cmd <- 01
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 201415 exit 0
Timestamp - device initialization: 74174874110
Initializing devices...
Root Device init ...
Root Device init finished in 1538 usecs
CPU_CLUSTER: 0 init ...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Enabling probe filter
Enabling ATM mode
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
start_eip=0x00001000, code_size=0x00000031
CPU1: stack_base 00151000, stack_end 00151ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
CPU: vendor AMD device 600f20
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
After Startup.
nodeid = 00, coreid = 01
CPU2: stack_base 00150000, stack_end 00150ff8
Enabling cache
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 2.
After apic_write.
Initializing CPU #2
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f20
After Startup.
CPU3: stack_base 0014f000, stack_end 0014fff8
CPU: family 15, model 02, stepping 00
Asserting INIT.
Waiting for send to finish...
+nodeid = 00, coreid = 02
Deasserting INIT.
Waiting for send to finish...
+Enabling cache
#startup loops: 1.
Sending STARTUP #1 to 3.
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
After apic_write.
MTRR: Physical address space:
Startup point 1.
Waiting for send to finish...
+Initializing CPU #3
After Startup.
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
CPU4: stack_base 0014e000, stack_end 0014eff8
CPU: vendor AMD device 600f20
Asserting INIT.
CPU: family 15, model 02, stepping 00
Waiting for send to finish...
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
Deasserting INIT.
0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
Waiting for send to finish...
+nodeid = 00, coreid = 03
#startup loops: 1.
Sending STARTUP #1 to 4.
After apic_write.
0x00000000c0000000 - 0x00000000e0000000 size 0x20000000 type 0
Startup point 1.
Waiting for send to finish...
+Initializing CPU #4
After Startup.
CPU5: stack_base 0014d000, stack_end 0014dff8
Enabling cache
Asserting INIT.
0x00000000e0000000 - 0x00000000f0200000 size 0x10200000 type 1
Waiting for send to finish...
0x00000000f0200000 - 0x0000000100000000 size 0x0fe00000 type 0
+0x0000000100000000 - 0x0000000840000000 size 0x740000000 type 6
Deasserting INIT.
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
Waiting for send to finish...
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
#startup loops: 1.
Sending STARTUP #1 to 5.
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
After apic_write.
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
Startup point 1.
Waiting for send to finish...
MTRR: default type WB/UC MTRR counts: 10/4.
+MTRR: UC selected as default type.
After Startup.
MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6
CPU6: stack_base 0014c000, stack_end 0014cff8
MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6
Asserting INIT.
MTRR: 2 base 0x00000000e0000000 mask 0x0000fffff0000000 type 1
MTRR: 3 base 0x00000000f0000000 mask 0x0000ffffffe00000 type 1
Waiting for send to finish...
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
+
Deasserting INIT.
Setting up local APIC...Waiting for send to finish...
+ apic_id: 0x02 done.
#startup loops: 1.
CPU model: AMD Opteron(tm) Processor 6386 SE
Sending STARTUP #1 to 6.
After apic_write.
siblings = 15, Startup point 1.
Disabling SMM ASeg memory
Waiting for send to finish...
+
MTRR check
After Startup.
CPU7: stack_base 0014b000, stack_end 0014bff8
CPU #2 initialized
Fixed MTRRs : Enabled
Asserting INIT.
Variable MTRRs: Enabled
Waiting for send to finish...
+
Deasserting INIT.
Setting up local APIC...Initializing CPU #6
apic_id: 0x03 done.
Waiting for send to finish...
CPU model: AMD Opteron(tm) Processor 6386 SE
+siblings = 15, #startup loops: 1.
Sending STARTUP #1 to 7.
Disabling SMM ASeg memory
After apic_write.
CPU #3 initialized
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f20
After Startup.
CPU8: stack_base 0014a000, stack_end 0014aff8
CPU: vendor AMD device 600f20
Asserting INIT.
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
Deasserting INIT.
Waiting for send to finish...
+Initializing CPU #7
#startup loops: 1.
Sending STARTUP #1 to 8.
After apic_write.
CPU: family 15, model 02, stepping 00
Startup point 1.
Waiting for send to finish...
+nodeid = 00, coreid = 06
After Startup.
CPU9: stack_base 00149000, stack_end 00149ff8
Initializing CPU #5
Asserting INIT.
Waiting for send to finish...
+Enabling cache
Deasserting INIT.
CPU: vendor AMD device 600f20
Waiting for send to finish...
+CPU: vendor AMD device 600f20
#startup loops: 1.
Sending STARTUP #1 to 9.
After apic_write.
CPU: family 15, model 02, stepping 00
Startup point 1.
Waiting for send to finish...
+nodeid = 00, coreid = 07
After Startup.
CPU10: stack_base 00148000, stack_end 00148ff8
CPU: family 15, model 02, stepping 00
Asserting INIT.
Enabling cache
Waiting for send to finish...
+CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Deasserting INIT.
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
Waiting for send to finish...
+MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
#startup loops: 1.
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
Sending STARTUP #1 to 10.
After apic_write.
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
Startup point 1.
Waiting for send to finish...
+Initializing CPU #10
After Startup.
MTRR check
CPU11: stack_base 00147000, stack_end 00147ff8
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Asserting INIT.
CPU: vendor AMD device 600f20
Waiting for send to finish...
+Setting up local APIC...Deasserting INIT.
apic_id: 0x06 Waiting for send to finish...
+done.
#startup loops: 1.
CPU model: AMD Opteron(tm) Processor 6386 SE
Sending STARTUP #1 to 11.
After apic_write.
siblings = 15, Startup point 1.
Waiting for send to finish...
+Disabling SMM ASeg memory
After Startup.
CPU12: stack_base 00146000, stack_end 00146ff8
CPU #6 initialized
Asserting INIT.
MTRR check
Waiting for send to finish...
+Fixed MTRRs : Deasserting INIT.
Enabled
Variable MTRRs: Enabled
Waiting for send to finish...
Setting up local APIC...+ apic_id: 0x07 #startup loops: 1.
Sending STARTUP #1 to 12.
done.
After apic_write.
CPU model: AMD Opteron(tm) Processor 6386 SE
Startup point 1.
Waiting for send to finish...
siblings = 15, +Disabling SMM ASeg memory
After Startup.
CPU13: stack_base 00145000, stack_end 00145ff8
CPU #7 initialized
Asserting INIT.
Initializing CPU #8
Waiting for send to finish...
+Initializing CPU #12
Deasserting INIT.
CPU: family 15, model 02, stepping 00
Waiting for send to finish...
+Initializing CPU #9
#startup loops: 1.
Sending STARTUP #1 to 13.
After apic_write.
CPU: vendor AMD device 600f20
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f20
After Startup.
CPU14: stack_base 00144000, stack_end 00144ff8
CPU: vendor AMD device 600f20
Asserting INIT.
Waiting for send to finish...
+Initializing CPU #11
Deasserting INIT.
Initializing CPU #13
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
#startup loops: 1.
Sending STARTUP #1 to 14.
After apic_write.
nodeid = 00, coreid = 05
Startup point 1.
Waiting for send to finish...
+Enabling cache
After Startup.
CPU15: stack_base 00143000, stack_end 00143ff8
Initializing CPU #14
Asserting INIT.
CPU: family 15, model 02, stepping 00
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
Deasserting INIT.
CPU: vendor AMD device 600f20
Waiting for send to finish...
+CPU: vendor AMD device 600f20
#startup loops: 1.
Sending STARTUP #1 to 15.
After apic_write.
CPU: family 15, model 02, stepping 00
Startup point 1.
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
After Startup.
CPU16: stack_base 00142000, stack_end 00142ff8
Initializing CPU #15
Asserting INIT.
Waiting for send to finish...
+nodeid = 01, coreid = 04
Deasserting INIT.
nodeid = 01, coreid = 01
Waiting for send to finish...
+nodeid = 00, coreid = 04
#startup loops: 1.
Sending STARTUP #1 to 32.
After apic_write.
nodeid = 01, coreid = 03
Startup point 1.
Waiting for send to finish...
+Initializing CPU #16
After Startup.
CPU17: stack_base 00141000, stack_end 00141ff8
Enabling cache
Asserting INIT.
nodeid = 01, coreid = 02
Waiting for send to finish...
+CPU: vendor AMD device 600f20
Deasserting INIT.
Waiting for send to finish...
+Enabling cache
#startup loops: 1.
Sending STARTUP #1 to 33.
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
After apic_write.
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
Startup point 1.
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
Waiting for send to finish...
+MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
After Startup.
CPU18: stack_base 00140000, stack_end 00140ff8
MTRR check
Fixed MTRRs : Enabled
Asserting INIT.
Variable MTRRs: Enabled
Waiting for send to finish...
+Setting up local APIC...Deasserting INIT.
apic_id: 0x04 Waiting for send to finish...
+done.
#startup loops: 1.
Sending STARTUP #1 to 34.
After apic_write.
CPU model: AMD Opteron(tm) Processor 6386 SE
Startup point 1.
Waiting for send to finish...
+siblings = 15, After Startup.
Disabling SMM ASeg memory
CPU19: stack_base 0013f000, stack_end 0013fff8
MTRR check
Fixed MTRRs : Asserting INIT.
CPU #4 initialized
Enabled
Waiting for send to finish...
Variable MTRRs: Enabled
+
Deasserting INIT.
Setting up local APIC...Waiting for send to finish...
+ apic_id: 0x05 done.
#startup loops: 1.
CPU model: AMD Opteron(tm) Processor 6386 SE
Sending STARTUP #1 to 35.
siblings = 15, After apic_write.
Disabling SMM ASeg memory
Startup point 1.
CPU #5 initialized
Waiting for send to finish...
+Initializing CPU #17
After Startup.
CPU20: stack_base 0013e000, stack_end 0013eff8
Enabling cache
Asserting INIT.
Waiting for send to finish...
+CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Deasserting INIT.
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
Waiting for send to finish...
+nodeid = 01, coreid = 06
#startup loops: 1.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Sending STARTUP #1 to 36.
Setting up local APIC...After apic_write.
apic_id: 0x0a done.
Startup point 1.
Waiting for send to finish...
CPU model: AMD Opteron(tm) Processor 6386 SE
+siblings = 15, After Startup.
CPU21: stack_base 0013d000, stack_end 0013dff8
Disabling SMM ASeg memory
Asserting INIT.
MTRR check
Fixed MTRRs : Waiting for send to finish...
+Enabled
Variable MTRRs: Enabled
CPU #10 initialized
Setting up local APIC...Deasserting INIT.
apic_id: 0x0b done.
Waiting for send to finish...
+CPU model: AMD Opteron(tm) Processor 6386 SE
#startup loops: 1.
siblings = 15, Sending STARTUP #1 to 37.
After apic_write.
Disabling SMM ASeg memory
Startup point 1.
Waiting for send to finish...
+CPU #11 initialized
After Startup.
CPU22: stack_base 0013c000, stack_end 0013cff8
Enabling cache
Asserting INIT.
CPU: vendor AMD device 600f20
Waiting for send to finish...
+nodeid = 01, coreid = 00
Deasserting INIT.
Enabling cache
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
#startup loops: 1.
Sending STARTUP #1 to 38.
After apic_write.
CPU: family 15, model 02, stepping 00
Startup point 1.
Waiting for send to finish...
+Enabling cache
After Startup.
CPU23: stack_base 0013b000, stack_end 0013bff8
Initializing CPU #20
Asserting INIT.
CPU: vendor AMD device 600f20
Waiting for send to finish...
+Enabling cache
Deasserting INIT.
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Waiting for send to finish...
+Initializing CPU #22
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
#startup loops: 1.
Sending STARTUP #1 to 39.
After apic_write.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Startup point 1.
Waiting for send to finish...
+Setting up local APIC...After Startup.
CPU24: stack_base 0013a000, stack_end 0013aff8
apic_id: 0x08 done.
Asserting INIT.
CPU model: AMD Opteron(tm) Processor 6386 SE
Waiting for send to finish...
+siblings = 15, Deasserting INIT.
Disabling SMM ASeg memory
Waiting for send to finish...
+CPU #8 initialized
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
#startup loops: 1.
Sending STARTUP #1 to 40.
Setting up local APIC...After apic_write.
apic_id: 0x09 done.
Startup point 1.
Waiting for send to finish...
+CPU model: AMD Opteron(tm) Processor 6386 SE
Initializing CPU #24
siblings = 15, After Startup.
Disabling SMM ASeg memory
CPU25: stack_base 00139000, stack_end 00139ff8
CPU #9 initialized
Asserting INIT.
Initializing CPU #21
Waiting for send to finish...
+CPU: vendor AMD device 600f20
Deasserting INIT.
CPU: family 15, model 02, stepping 00
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
#startup loops: 1.
Sending STARTUP #1 to 41.
After apic_write.
nodeid = 01, coreid = 05
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Startup point 1.
Waiting for send to finish...
+Enabling cache
After Startup.
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
CPU26: stack_base 00138000, stack_end 00138ff8
Initializing CPU #19
Asserting INIT.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Waiting for send to finish...
+Setting up local APIC...Deasserting INIT.
apic_id: 0x0c done.
Waiting for send to finish...
+CPU model: AMD Opteron(tm) Processor 6386 SE
Initializing CPU #18
#startup loops: 1.
Sending STARTUP #1 to 42.
siblings = 15, After apic_write.
Disabling SMM ASeg memory
Startup point 1.
Waiting for send to finish...
+
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
After Startup.
CPU27: stack_base 00137000, stack_end 00137ff8
CPU #12 initialized
Setting up local APIC...Asserting INIT.
apic_id: 0x0d done.
Waiting for send to finish...
+CPU model: AMD Opteron(tm) Processor 6386 SE
Initializing CPU #26
Deasserting INIT.
siblings = 15, Waiting for send to finish...
+Disabling SMM ASeg memory
#startup loops: 1.
Sending STARTUP #1 to 43.
After apic_write.
CPU #13 initialized
Startup point 1.
Waiting for send to finish...
+nodeid = 01, coreid = 07
After Startup.
CPU28: stack_base 00136000, stack_end 00136ff8
Enabling cache
Asserting INIT.
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Waiting for send to finish...
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
+nodeid = 03, coreid = 00
Deasserting INIT.
CPU: vendor AMD device 600f20
Waiting for send to finish...
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
+CPU: vendor AMD device 600f20
#startup loops: 1.
Sending STARTUP #1 to 44.
After apic_write.
Setting up local APIC...Startup point 1.
apic_id: 0x0e done.
Waiting for send to finish...
+CPU model: AMD Opteron(tm) Processor 6386 SE
After Startup.
siblings = 15, CPU29: stack_base 00135000, stack_end 00135ff8
Disabling SMM ASeg memory
Asserting INIT.
CPU #14 initialized
Waiting for send to finish...
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
+Initializing CPU #28
Deasserting INIT.
Setting up local APIC...Waiting for send to finish...
apic_id: 0x0f done.
+CPU model: AMD Opteron(tm) Processor 6386 SE
#startup loops: 1.
Sending STARTUP #1 to 45.
After apic_write.
siblings = 15, Startup point 1.
Waiting for send to finish...
Disabling SMM ASeg memory
+CPU #15 initialized
After Startup.
CPU30: stack_base 00134000, stack_end 00134ff8
CPU: vendor AMD device 600f20
Asserting INIT.
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
Deasserting INIT.
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
#startup loops: 1.
Sending STARTUP #1 to 46.
After apic_write.
CPU: vendor AMD device 600f20
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 600f20
After Startup.
CPU31: stack_base 00133000, stack_end 00133ff8
CPU: vendor AMD device 600f20
Asserting INIT.
nodeid = 02, coreid = 06
Waiting for send to finish...
+Initializing CPU #30
Deasserting INIT.
Initializing CPU #23
Waiting for send to finish...
+CPU: vendor AMD device 600f20
#startup loops: 1.
Sending STARTUP #1 to 47.
After apic_write.
CPU: family 15, model 02, stepping 00
Startup point 1.
Waiting for send to finish...
+CPU: family 15, model 02, stepping 00
After Startup.
Initializing CPU #0
CPU: vendor AMD device 600f20
CPU: family 15, model 02, stepping 00
Initializing CPU #29
nodeid = 00, coreid = 00
Enabling cache
nodeid = 02, coreid = 03
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
nodeid = 02, coreid = 00
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
nodeid = 02, coreid = 02
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Enabling cache
Setting up local APIC...Initializing CPU #25
apic_id: 0x00 done.
Enabling cache
CPU model: AMD Opteron(tm) Processor 6386 SE
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
siblings = 15, Enabling cache
Disabling SMM ASeg memory
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
CPU #0 initialized
Waiting for 17 CPUS to stop
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC...Setting up local APIC... apic_id: 0x01 done.
apic_id: 0x22 done.
CPU model: AMD Opteron(tm) Processor 6386 SE
CPU model: AMD Opteron(tm) Processor 6386 SE
siblings = 15, siblings = 15, Disabling SMM ASeg memory
Disabling SMM ASeg memory
CPU #1 initialized
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Waiting for 16 CPUS to stop
Setting up local APIC...CPU #18 initialized
apic_id: 0x23 done.
Waiting for 15 CPUS to stop
CPU model: AMD Opteron(tm) Processor 6386 SE
CPU: vendor AMD device 600f20
siblings = 15, CPU: family 15, model 02, stepping 00
Disabling SMM ASeg memory
CPU: vendor AMD device 600f20
CPU #19 initialized
CPU: family 15, model 02, stepping 00
Waiting for 14 CPUS to stop
nodeid = 03, coreid = 01
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
CPU: vendor AMD device 600f20
Enabling cache
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
CPU: family 15, model 02, stepping 00
CPU: vendor AMD device 600f20
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Initializing CPU #27
Setting up local APIC...nodeid = 02, coreid = 01
apic_id: 0x28 done.
Initializing CPU #31
CPU model: AMD Opteron(tm) Processor 6386 SE
CPU: family 15, model 02, stepping 00
siblings = 15, CPU: family 15, model 02, stepping 00
Disabling SMM ASeg memory
CPU: family 15, model 02, stepping 00
MTRR check
CPU #24 initialized
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Waiting for 13 CPUS to stop
Setting up local APIC...Enabling cache
apic_id: 0x29 done.
nodeid = 02, coreid = 07
CPU model: AMD Opteron(tm) Processor 6386 SE
Enabling cache
siblings = 15, Enabling cache
Disabling SMM ASeg memory
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
CPU #25 initialized
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
Waiting for 12 CPUS to stop
Enabling cache
CPU: vendor AMD device 600f20
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Setting up local APIC...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
apic_id: 0x26 done.
CPU: family 15, model 02, stepping 00
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU model: AMD Opteron(tm) Processor 6386 SE
Setting up local APIC...siblings = 15, apic_id: 0x20 done.
Disabling SMM ASeg memory
CPU model: AMD Opteron(tm) Processor 6386 SE
MTRR check
CPU #22 initialized
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Waiting for 11 CPUS to stop
siblings = 15, Setting up local APIC...Disabling SMM ASeg memory
apic_id: 0x27 done.
CPU #16 initialized
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Waiting for 10 CPUS to stop
Setting up local APIC...CPU model: AMD Opteron(tm) Processor 6386 SE
apic_id: 0x21 done.
siblings = 15, CPU model: AMD Opteron(tm) Processor 6386 SE
Disabling SMM ASeg memory
siblings = 15, CPU #23 initialized
Disabling SMM ASeg memory
Waiting for 9 CPUS to stop
CPU #17 initialized
CPU: vendor AMD device 600f20
Waiting for 8 CPUS to stop
CPU: family 15, model 02, stepping 00
nodeid = 02, coreid = 05
CPU: vendor AMD device 600f20
Enabling cache
CPU: family 15, model 02, stepping 00
nodeid = 02, coreid = 04
nodeid = 03, coreid = 07
nodeid = 03, coreid = 06
nodeid = 03, coreid = 03
nodeid = 03, coreid = 05
Enabling cache
CPU: family 15, model 02, stepping 00
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Enabling cache
Enabling cache
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
Enabling cache
Enabling cache
nodeid = 03, coreid = 04
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Setting up local APIC...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
apic_id: 0x24 done.
Enabling cache
CPU model: AMD Opteron(tm) Processor 6386 SE
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
siblings = 15, Setting up local APIC...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
apic_id: 0x2e done.
Disabling SMM ASeg memory
CPU model: AMD Opteron(tm) Processor 6386 SE
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
siblings = 15, CPU #20 initialized
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC...Disabling SMM ASeg memory
Waiting for 7 CPUS to stop
Setting up local APIC...
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
apic_id: 0x2c done.
CPU #30 initialized
Setting up local APIC...CPU model: AMD Opteron(tm) Processor 6386 SE
Waiting for 6 CPUS to stop
apic_id: 0x2f done.
siblings = 15, CPU model: AMD Opteron(tm) Processor 6386 SE
apic_id: 0x25 done.
Disabling SMM ASeg memory
siblings = 15,
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU #28 initialized
Setting up local APIC...Disabling SMM ASeg memory
apic_id: 0x2d done.
Waiting for 5 CPUS to stop
CPU model: AMD Opteron(tm) Processor 6386 SE
CPU model: AMD Opteron(tm) Processor 6386 SE
siblings = 15, siblings = 15, CPU #31 initialized
Disabling SMM ASeg memory
Waiting for 4 CPUS to stop
Disabling SMM ASeg memory
CPU #29 initialized
CPU #21 initialized
Waiting for 3 CPUS to stop
nodeid = 03, coreid = 02
Waiting for 2 CPUS to stop
Enabling cache
CPU ID 0x80000001: 600f20
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x2a done.
CPU model: AMD Opteron(tm) Processor 6386 SE
siblings = 15, Disabling SMM ASeg memory
CPU #26 initialized
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Waiting for 1 CPUS to stop
Setting up local APIC... apic_id: 0x2b done.
CPU model: AMD Opteron(tm) Processor 6386 SE
siblings = 15, Disabling SMM ASeg memory
CPU #27 initialized
All AP CPUs stopped (66836 loops)
CPU0: stack: 00152000 - 00153000, lowest used address 001529b0, stack used: 1616 bytes
CPU1: stack: 00151000 - 00152000, lowest used address 00151dd0, stack used: 560 bytes
CPU2: stack: 00150000 - 00151000, lowest used address 00150c90, stack used: 880 bytes
CPU3: stack: 0014f000 - 00150000, lowest used address 0014fdd0, stack used: 560 bytes
CPU4: stack: 0014e000 - 0014f000, lowest used address 0014ecf0, stack used: 784 bytes
CPU5: stack: 0014d000 - 0014e000, lowest used address 0014ddd0, stack used: 560 bytes
CPU6: stack: 0014c000 - 0014d000, lowest used address 0014ccf0, stack used: 784 bytes
CPU7: stack: 0014b000 - 0014c000, lowest used address 0014bdd0, stack used: 560 bytes
CPU8: stack: 0014a000 - 0014b000, lowest used address 0014acf0, stack used: 784 bytes
CPU9: stack: 00149000 - 0014a000, lowest used address 00149dd0, stack used: 560 bytes
CPU10: stack: 00148000 - 00149000, lowest used address 00148cf0, stack used: 784 bytes
CPU11: stack: 00147000 - 00148000, lowest used address 00147dd0, stack used: 560 bytes
CPU12: stack: 00146000 - 00147000, lowest used address 00146cf0, stack used: 784 bytes
CPU13: stack: 00145000 - 00146000, lowest used address 00145dd0, stack used: 560 bytes
CPU14: stack: 00144000 - 00145000, lowest used address 00144cf0, stack used: 784 bytes
CPU15: stack: 00143000 - 00144000, lowest used address 00143dd0, stack used: 560 bytes
CPU16: stack: 00142000 - 00143000, lowest used address 00142cf0, stack used: 784 bytes
CPU17: stack: 00141000 - 00142000, lowest used address 00141dd0, stack used: 560 bytes
CPU18: stack: 00140000 - 00141000, lowest used address 00140cf0, stack used: 784 bytes
CPU19: stack: 0013f000 - 00140000, lowest used address 0013fdd0, stack used: 560 bytes
CPU20: stack: 0013e000 - 0013f000, lowest used address 0013ecf0, stack used: 784 bytes
CPU21: stack: 0013d000 - 0013e000, lowest used address 0013ddd0, stack used: 560 bytes
CPU22: stack: 0013c000 - 0013d000, lowest used address 0013ccf0, stack used: 784 bytes
CPU23: stack: 0013b000 - 0013c000, lowest used address 0013bdd0, stack used: 560 bytes
CPU24: stack: 0013a000 - 0013b000, lowest used address 0013acf0, stack used: 784 bytes
CPU25: stack: 00139000 - 0013a000, lowest used address 00139dd0, stack used: 560 bytes
CPU26: stack: 00138000 - 00139000, lowest used address 00138cf0, stack used: 784 bytes
CPU27: stack: 00137000 - 00138000, lowest used address 00137dd0, stack used: 560 bytes
CPU28: stack: 00136000 - 00137000, lowest used address 00136cf0, stack used: 784 bytes
CPU29: stack: 00135000 - 00136000, lowest used address 00135dd0, stack used: 560 bytes
CPU30: stack: 00134000 - 00135000, lowest used address 00134cf0, stack used: 784 bytes
CPU31: stack: 00133000 - 00134000, lowest used address 00133dd0, stack used: 560 bytes
CPU_CLUSTER: 0 init finished in 2361064 usecs
PCI: 00:18.0 init ...
PCI: 00:18.0 init finished in 1608 usecs
PCI: 00:18.1 init ...
PCI: 00:18.1 init finished in 1608 usecs
PCI: 00:18.2 init ...
PCI: 00:18.2 init finished in 1608 usecs
PCI: 00:18.3 init ...
NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:18.3 init finished in 14213 usecs
PCI: 00:18.4 init ...
NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:18.4 init finished in 23872 usecs
PCI: 00:18.5 init ...
NB: Function 5 Northbridge Control.. done.
PCI: 00:18.5 init finished in 4687 usecs
PCI: 00:19.0 init ...
PCI: 00:19.0 init finished in 1608 usecs
PCI: 00:19.1 init ...
PCI: 00:19.1 init finished in 1608 usecs
PCI: 00:19.2 init ...
PCI: 00:19.2 init finished in 1608 usecs
PCI: 00:19.3 init ...
NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:19.3 init finished in 14214 usecs
PCI: 00:19.4 init ...
NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:19.4 init finished in 23871 usecs
PCI: 00:19.5 init ...
NB: Function 5 Northbridge Control.. done.
PCI: 00:19.5 init finished in 4686 usecs
PCI: 00:1a.0 init ...
PCI: 00:1a.0 init finished in 1609 usecs
PCI: 00:1a.1 init ...
PCI: 00:1a.1 init finished in 1609 usecs
PCI: 00:1a.2 init ...
PCI: 00:1a.2 init finished in 1608 usecs
PCI: 00:1a.3 init ...
NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:1a.3 init finished in 14213 usecs
PCI: 00:1a.4 init ...
NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:1a.4 init finished in 23871 usecs
PCI: 00:1a.5 init ...
NB: Function 5 Northbridge Control.. done.
PCI: 00:1a.5 init finished in 4687 usecs
PCI: 00:1b.0 init ...
PCI: 00:1b.0 init finished in 1608 usecs
PCI: 00:1b.1 init ...
PCI: 00:1b.1 init finished in 1609 usecs
PCI: 00:1b.2 init ...
PCI: 00:1b.2 init finished in 1607 usecs
PCI: 00:1b.3 init ...
NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:1b.3 init finished in 14214 usecs
PCI: 00:1b.4 init ...
NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
done.
PCI: 00:1b.4 init finished in 23871 usecs
PCI: 00:1b.5 init ...
NB: Function 5 Northbridge Control.. done.
PCI: 00:1b.5 init finished in 4687 usecs
PCI: 00:00.0 init ...
pcie_init in sr5650_ht.c
IOAPIC: Initializing IOAPIC at 0xf0200000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x01
IOAPIC: Dumping registers
reg 0x0000: 0x01000000
reg 0x0001: 0x001f8021
reg 0x0002: 0x00000000
IOAPIC: 32 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
PCI: 00:00.0 init finished in 138294 usecs
PCI: 00:11.0 init ...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
rev_id=15
sata_bar0=5020
sata_bar1=5040
sata_bar2=5028
sata_bar3=5044
sata_bar4=5000
sata_bar5=f840d000
ide_bar0=5030
ide_bar1=5048
ide_bar2=5038
ide_bar3=504c
Maximum SATA port count supported by silicon: 6
SATA port 0 status = 13
drive detection done after 0 ms
AHCI device 0 is ready after 1 tries
SATA port 1 status = 23
0x6=b0, 0x7=80
drive detection not yet completed, waiting...
0x6=10, 0x7=50
drive no longer selected after 10 ms, retrying init
drive detection done after 0 ms
AHCI device 1 is ready after 2 tries
SATA port 2 status = 23
drive detection done after 0 ms
AHCI device 2 is ready after 1 tries
SATA port 3 status = 0
No AHCI SATA drive on Slot3
SATA port 4 status = 0
No AHCI SATA drive on Slot4
SATA port 5 status = 0
No AHCI SATA drive on Slot5
PCI: 00:11.0 init finished in 94789 usecs
PCI: 00:12.0 init ...
PCI: 00:12.0 init finished in 1633 usecs
PCI: 00:12.1 init ...
PCI: 00:12.1 init finished in 1632 usecs
PCI: 00:12.2 init ...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
usb2_bar0=0xf840e000
rpr 6.23, final dword=849e03c8
PCI: 00:12.2 init finished in 15329 usecs
PCI: 00:13.0 init ...
PCI: 00:13.0 init finished in 1631 usecs
PCI: 00:13.1 init ...
PCI: 00:13.1 init finished in 1633 usecs
PCI: 00:13.2 init ...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
usb2_bar0=0xf840f000
rpr 6.23, final dword=849e03c8
PCI: 00:13.2 init finished in 15329 usecs
PCI: 00:14.0 init ...
sm_init().
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: Dumping registers
reg 0x0000: 0x00000000
reg 0x0001: 0x00178021
reg 0x0002: 0x00000000
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
WARNING: No CMOS option 'enable_legacy_usb'.
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
set power "on" after power fail
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
++++++++++no set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.0 init finished in 145821 usecs
PCI: 00:14.1 init ...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
PCI: 00:14.1 init finished in 11463 usecs
PCI: 00:14.2 init ...
base = 0xf8404000
No codec!
PCI: 00:14.2 init finished in 6927 usecs
PCI: 00:14.3 init ...
lpc_init
PCI: 00:14.3 init finished in 2339 usecs
PCI: 00:14.4 init ...
PCI: 00:14.4 init finished in 1628 usecs
PCI: 00:14.5 init ...
PCI: 00:14.5 init finished in 1632 usecs
PCI: 03:00.0 init ...
PCI: 03:00.0 init finished in 1608 usecs
PCI: 04:00.0 init ...
PCI: 04:00.0 init finished in 1608 usecs
PCI: 05:00.0 init ...
PCI: 05:00.0 init finished in 1608 usecs
PCI: 05:00.1 init ...
PCI: 05:00.1 init finished in 1608 usecs
PCI: 07:00.0 init ...
PCI: 07:00.0 init finished in 1608 usecs
smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
Set SMBUS controller to channel 1
Found 64 pin W83795G Nuvoton H/W Monitor
W83795G/ADG work in Thermal Cruise Mode
Fan CTFS(celsius) TTTI(celsius)
1 80 80
2 80 80
3 80 80
4 80 80
5 80 80
6 80 80
DTS1 current value: 17
DTS2 current value: 13
DTS3 current value: 0
DTS4 current value: 0
DTS5 current value: 0
DTS6 current value: 0
DTS7 current value: 0
DTS8 current value: 0
Set SMBUS controller to channel 0
I2C: 01:2f init finished in 312059 usecs
PNP: 002e.2 init ...
PNP: 002e.2 init finished in 1540 usecs
PNP: 002e.3 init ...
PNP: 002e.3 init finished in 1539 usecs
PNP: 002e.5 init ...
w83667hg_a_init: Disable mouse controller.PNP: 002e.5 init finished in 4479 usecs
PNP: 002e.a init ...
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
set power on after power fail
PNP: 002e.a init finished in 13394 usecs
PNP: 002e.b init ...
PNP: 002e.b init finished in 1538 usecs
PCI: 08:03.0 init ...
PCI: 08:03.0 init finished in 1608 usecs
PCI: 08:03.1 init ...
PCI: 08:03.1 init finished in 1608 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 0
PCI: 00:00.2: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:0c.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 01:50: enabled 1
I2C: 01:51: enabled 1
I2C: 01:52: enabled 1
I2C: 01:53: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:2f: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.106: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 0
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.108: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 0
PNP: 002e.f: enabled 0
PNP: 004e.0: enabled 1
PCI: 00:14.4: enabled 1
PCI: 08:01.0: enabled 0
PCI: 08:02.0: enabled 0
PCI: 08:03.0: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:19.1: enabled 1
PCI: 00:19.2: enabled 1
PCI: 00:19.3: enabled 1
PCI: 00:19.4: enabled 1
PCI: 00:19.5: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1a.1: enabled 1
PCI: 00:1a.2: enabled 1
PCI: 00:1a.3: enabled 1
PCI: 00:1a.4: enabled 1
PCI: 00:1a.5: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1b.1: enabled 1
PCI: 00:1b.2: enabled 1
PCI: 00:1b.3: enabled 1
PCI: 00:1b.4: enabled 1
PCI: 00:1b.5: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
APIC: 06: enabled 1
APIC: 07: enabled 1
APIC: 08: enabled 1
APIC: 09: enabled 1
APIC: 0a: enabled 1
APIC: 0b: enabled 1
APIC: 0c: enabled 1
APIC: 0d: enabled 1
APIC: 0e: enabled 1
APIC: 0f: enabled 1
APIC: 20: enabled 1
APIC: 21: enabled 1
APIC: 22: enabled 1
APIC: 23: enabled 1
APIC: 24: enabled 1
APIC: 25: enabled 1
APIC: 26: enabled 1
APIC: 27: enabled 1
APIC: 28: enabled 1
APIC: 29: enabled 1
APIC: 2a: enabled 1
APIC: 2b: enabled 1
APIC: 2c: enabled 1
APIC: 2d: enabled 1
APIC: 2e: enabled 1
APIC: 2f: enabled 1
PCI: 03:00.0: enabled 1
PCI: 04:00.0: enabled 1
PCI: 05:00.0: enabled 1
PCI: 05:00.1: enabled 1
PCI: 07:00.0: enabled 1
PCI: 08:03.1: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 3715212 exit 0
Finalize devices...
Devices finalized
Timestamp - device setup done: 87201742439
BS: BS_POST_DEVICE times (us): entry 0 run 5865 exit 0
Timestamp - cbmem post: 87226107616
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2579 exit 0
Timestamp - write tables: 87249741252
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
Writing IRQ routing tables to 0xf0000...done.
Writing IRQ routing tables to 0xbfcbe000...done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f08ac
Wrote the mp table end at: bfcbd010 - bfcbd4ac
MP table: 1196 bytes.
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 2cc40 size 26a7
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at bfc99000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * FADT
pm_base: 0x0800
ACPI: added table 1/32, length now 40
ACPI: * SSDT
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
processor_brand=AMD Opteron(tm) Processor 6386 SE
Pstates algorithm ...
Pstate_freq[0] = 2800MHz Pstate_power[0] = 7612mw
Pstate_latency[0] = 5us
Pstate_freq[1] = 2500MHz Pstate_power[1] = 6615mw
Pstate_latency[1] = 5us
Pstate_freq[2] = 2200MHz Pstate_power[2] = 5670mw
Pstate_latency[2] = 5us
Pstate_freq[3] = 1800MHz Pstate_power[3] = 4370mw
Pstate_latency[3] = 5us
Pstate_freq[4] = 1400MHz Pstate_power[4] = 3283mw
Pstate_latency[4] = 5us
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
PSS: 2800MHz power 7612 control 0x0 status 0x0
PSS: 2500MHz power 6615 control 0x1 status 0x1
PSS: 2200MHz power 5670 control 0x2 status 0x2
PSS: 1800MHz power 4370 control 0x3 status 0x3
PSS: 1400MHz power 3283 control 0x4 status 0x4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'pci1002,67ef.rom'
CBFS: 'pci1002,67ef.rom' not found.
PCI Option ROM loading disabled for PCI: 05:00.0
PCI: 05:00.0: Missing PCI Option ROM
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TCPA
TCPA log created at bfc89000
ACPI: added table 4/32, length now 52
ACPI: * MADT
ACPI: added table 5/32, length now 56
current = bfc9f4b0
ACPI: * SRAT at bfc9f4b0
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
SRAT: lapic cpu_index=06, node_id=00, apic_id=06
SRAT: lapic cpu_index=07, node_id=00, apic_id=07
SRAT: lapic cpu_index=08, node_id=01, apic_id=08
SRAT: lapic cpu_index=09, node_id=01, apic_id=09
SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
SRAT: lapic cpu_index=10, node_id=02, apic_id=20
SRAT: lapic cpu_index=11, node_id=02, apic_id=21
SRAT: lapic cpu_index=12, node_id=02, apic_id=22
SRAT: lapic cpu_index=13, node_id=02, apic_id=23
SRAT: lapic cpu_index=14, node_id=02, apic_id=24
SRAT: lapic cpu_index=15, node_id=02, apic_id=25
SRAT: lapic cpu_index=16, node_id=02, apic_id=26
SRAT: lapic cpu_index=17, node_id=02, apic_id=27
SRAT: lapic cpu_index=18, node_id=03, apic_id=28
SRAT: lapic cpu_index=19, node_id=03, apic_id=29
SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000
set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000
ACPI: added table 6/32, length now 60
ACPI: * SLIT at bfc9f780
ACPI: added table 7/32, length now 64
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
ACPI: * IVRS at bfc9f7c0
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x09 @ 0x48
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x09 @ 0x48
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0xdc
Capability: type 0x01 @ 0xdc
ACPI: added table 8/32, length now 68
ACPI: * HPET
ACPI: added table 9/32, length now 72
ACPI: * SRAT at bfc9f8c0
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
SRAT: lapic cpu_index=06, node_id=00, apic_id=06
SRAT: lapic cpu_index=07, node_id=00, apic_id=07
SRAT: lapic cpu_index=08, node_id=01, apic_id=08
SRAT: lapic cpu_index=09, node_id=01, apic_id=09
SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
SRAT: lapic cpu_index=10, node_id=02, apic_id=20
SRAT: lapic cpu_index=11, node_id=02, apic_id=21
SRAT: lapic cpu_index=12, node_id=02, apic_id=22
SRAT: lapic cpu_index=13, node_id=02, apic_id=23
SRAT: lapic cpu_index=14, node_id=02, apic_id=24
SRAT: lapic cpu_index=15, node_id=02, apic_id=25
SRAT: lapic cpu_index=16, node_id=02, apic_id=26
SRAT: lapic cpu_index=17, node_id=02, apic_id=27
SRAT: lapic cpu_index=18, node_id=03, apic_id=28
SRAT: lapic cpu_index=19, node_id=03, apic_id=29
SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000
set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000
ACPI: added table 10/32, length now 76
ACPI: * SLIT at bfc9fb90
ACPI: added table 11/32, length now 80
ACPI: * SRAT at bfc9fbd0
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
SRAT: lapic cpu_index=06, node_id=00, apic_id=06
SRAT: lapic cpu_index=07, node_id=00, apic_id=07
SRAT: lapic cpu_index=08, node_id=01, apic_id=08
SRAT: lapic cpu_index=09, node_id=01, apic_id=09
SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
SRAT: lapic cpu_index=10, node_id=02, apic_id=20
SRAT: lapic cpu_index=11, node_id=02, apic_id=21
SRAT: lapic cpu_index=12, node_id=02, apic_id=22
SRAT: lapic cpu_index=13, node_id=02, apic_id=23
SRAT: lapic cpu_index=14, node_id=02, apic_id=24
SRAT: lapic cpu_index=15, node_id=02, apic_id=25
SRAT: lapic cpu_index=16, node_id=02, apic_id=26
SRAT: lapic cpu_index=17, node_id=02, apic_id=27
SRAT: lapic cpu_index=18, node_id=03, apic_id=28
SRAT: lapic cpu_index=19, node_id=03, apic_id=29
SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000
set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000
ACPI: added table 12/32, length now 84
ACPI: * SLIT at bfc9fea0
ACPI: added table 13/32, length now 88
ACPI: * SRAT at bfc9fee0
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
SRAT: lapic cpu_index=06, node_id=00, apic_id=06
SRAT: lapic cpu_index=07, node_id=00, apic_id=07
SRAT: lapic cpu_index=08, node_id=01, apic_id=08
SRAT: lapic cpu_index=09, node_id=01, apic_id=09
SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
SRAT: lapic cpu_index=10, node_id=02, apic_id=20
SRAT: lapic cpu_index=11, node_id=02, apic_id=21
SRAT: lapic cpu_index=12, node_id=02, apic_id=22
SRAT: lapic cpu_index=13, node_id=02, apic_id=23
SRAT: lapic cpu_index=14, node_id=02, apic_id=24
SRAT: lapic cpu_index=15, node_id=02, apic_id=25
SRAT: lapic cpu_index=16, node_id=02, apic_id=26
SRAT: lapic cpu_index=17, node_id=02, apic_id=27
SRAT: lapic cpu_index=18, node_id=03, apic_id=28
SRAT: lapic cpu_index=19, node_id=03, apic_id=29
SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000
set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000
ACPI: added table 14/32, length now 92
ACPI: * SLIT at bfca01b0
ACPI: added table 15/32, length now 96
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'pci1002,67ef.rom'
CBFS: 'pci1002,67ef.rom' not found.
PCI Option ROM loading disabled for PCI: 05:00.0
ACPI: done.
ACPI tables: 29168 bytes.
smbios_write_tables: bfc88000
Root Device (ASUS KGPE-D16)
CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
APIC: 00 (unknown)
DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
PCI: 00:00.0 (ATI SR5650)
PCI: 00:00.1 (ATI SR5650)
PCI: 00:00.2 (ATI SR5650)
PCI: 00:02.0 (ATI SR5650)
PCI: 00:03.0 (ATI SR5650)
PCI: 00:04.0 (ATI SR5650)
PCI: 00:05.0 (ATI SR5650)
PCI: 00:06.0 (ATI SR5650)
PCI: 00:07.0 (ATI SR5650)
PCI: 00:08.0 (ATI SR5650)
PCI: 00:09.0 (ATI SR5650)
PCI: 00:0a.0 (ATI SR5650)
PCI: 00:0b.0 (ATI SR5650)
PCI: 00:0c.0 (ATI SR5650)
PCI: 00:0d.0 (ATI SR5650)
PCI: 00:11.0 (ATI SP5100)
PCI: 00:12.0 (ATI SP5100)
PCI: 00:12.1 (ATI SP5100)
PCI: 00:12.2 (ATI SP5100)
PCI: 00:13.0 (ATI SP5100)
PCI: 00:13.1 (ATI SP5100)
PCI: 00:13.2 (ATI SP5100)
PCI: 00:14.0 (ATI SP5100)
I2C: 01:50 (unknown)
I2C: 01:51 (unknown)
I2C: 01:52 (unknown)
I2C: 01:53 (unknown)
I2C: 01:54 (unknown)
I2C: 01:55 (unknown)
I2C: 01:56 (unknown)
I2C: 01:57 (unknown)
I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
PCI: 00:14.1 (ATI SP5100)
PCI: 00:14.2 (ATI SP5100)
PCI: 00:14.3 (ATI SP5100)
PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
PNP: 002e.a (WINBOND W83667HG-A Super I/O)
PNP: 002e.b (WINBOND W83667HG-A Super I/O)
PNP: 002e.c (WINBOND W83667HG-A Super I/O)
PNP: 002e.d (WINBOND W83667HG-A Super I/O)
PNP: 002e.f (WINBOND W83667HG-A Super I/O)
PNP: 004e.0 (unknown)
PCI: 00:14.4 (ATI SP5100)
PCI: 08:01.0 (ATI SP5100)
PCI: 08:02.0 (ATI SP5100)
PCI: 08:03.0 (ATI SP5100)
PCI: 00:14.5 (ATI SP5100)
PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
PCI: 00:1a.0 (AMD Family 10h/15h Northbridge)
PCI: 00:1a.1 (AMD Family 10h/15h Northbridge)
PCI: 00:1a.2 (AMD Family 10h/15h Northbridge)
PCI: 00:1a.3 (AMD Family 10h/15h Northbridge)
PCI: 00:1a.4 (AMD Family 10h/15h Northbridge)
PCI: 00:1a.5 (AMD Family 10h/15h Northbridge)
PCI: 00:1b.0 (AMD Family 10h/15h Northbridge)
PCI: 00:1b.1 (AMD Family 10h/15h Northbridge)
PCI: 00:1b.2 (AMD Family 10h/15h Northbridge)
PCI: 00:1b.3 (AMD Family 10h/15h Northbridge)
PCI: 00:1b.4 (AMD Family 10h/15h Northbridge)
PCI: 00:1b.5 (AMD Family 10h/15h Northbridge)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
APIC: 06 (unknown)
APIC: 07 (unknown)
APIC: 08 (unknown)
APIC: 09 (unknown)
APIC: 0a (unknown)
APIC: 0b (unknown)
APIC: 0c (unknown)
APIC: 0d (unknown)
APIC: 0e (unknown)
APIC: 0f (unknown)
APIC: 20 (unknown)
APIC: 21 (unknown)
APIC: 22 (unknown)
APIC: 23 (unknown)
APIC: 24 (unknown)
APIC: 25 (unknown)
APIC: 26 (unknown)
APIC: 27 (unknown)
APIC: 28 (unknown)
APIC: 29 (unknown)
APIC: 2a (unknown)
APIC: 2b (unknown)
APIC: 2c (unknown)
APIC: 2d (unknown)
APIC: 2e (unknown)
APIC: 2f (unknown)
PCI: 03:00.0 (unknown)
PCI: 04:00.0 (unknown)
PCI: 05:00.0 (unknown)
PCI: 05:00.1 (unknown)
PCI: 07:00.0 (unknown)
PCI: 08:03.1 (unknown)
SMBIOS tables: 571 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5012
Writing coreboot table at 0xbfcbf000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-00000000000fffff: RAM
2. 0000000000100000-0000000000218fff: RAMSTAGE
3. 0000000000219000-00000000bfc87fff: RAM
4. 00000000bfc88000-00000000bfffffff: CONFIGURATION TABLES
5. 00000000c0000000-00000000cfffffff: RESERVED
6. 00000000f8400000-00000000f8403fff: RESERVED
7. 00000000feb00000-00000000feb00fff: RESERVED
8. 00000000fec00000-00000000fec00fff: RESERVED
9. 00000000fed00000-00000000fed00fff: RESERVED
10. 0000000100000000-000000083fffffff: RAM
Manufacturer: ef
SF: Detected W25Q128 with sector size 0x1000, total 0x1000000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
FMAP: Found "FLASH" version 1.1 at 0.
FMAP: base = ff000000 size = 1000000 #areas = 3
Wrote coreboot table at: bfcbf000, 0x1124 bytes, checksum 5806
coreboot table: 4412 bytes.
IMD ROOT 0. bffff000 00001000
IMD SMALL 1. bfffe000 00001000
CAR GLOBALS 2. bfff3000 0000a6c0
CONSOLE 3. bffd3000 00020000
TIME STAMP 4. bffd2000 00000910
AMDMEM INFO 5. bffc8000 000093fc
ACPI RESUME 6. bfcc7000 00301000
COREBOOT 7. bfcbf000 00008000
IRQ TABLE 8. bfcbe000 00001000
SMP TABLE 9. bfcbd000 00001000
ACPI 10. bfc99000 00024000
TCPA LOG 11. bfc89000 00010000
SMBIOS 12. bfc88000 00000800
IMD small region:
IMD ROOT 0. bfffec00 00000400
ROMSTAGE 1. bfffebe0 00000004
GDT 2. bfffe9e0 00000200
COREBOOTFWD 3. bfffe9a0 00000028
Timestamp - finalize chips: 93385183042
Writing AMD DCT configuration to Flash
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 's3nv'
CBFS: Found @ offset 2fdc0 size 10000
Manufacturer: ef
SF: Detected W25Q128 with sector size 0x1000, total 0x1000000
SF: Successfully erased 32768 bytes @ 0x38000
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 2be40 size dc4
BS: BS_WRITE_TABLES times (us): entry 0 run 2379206 exit 0
Timestamp - load payload: 95612910694
CBFS: 'Master Header Locator' located CBFS at [200:ffffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 71f40 size 17b02
Loading segment from ROM address 0xff072178
code (compression=2)
New segment dstaddr 0xdcdc0 memsize 0x23240 srcaddr 0xff0721b0 filesize 0x17aca
Loading segment from ROM address 0xff072194
Entry Point 0x000fcac9
Bounce Buffer at bfa57000, 2295408 bytes
Loading Segment: addr: 0x00000000000dcdc0 memsz: 0x0000000000023240 filesz: 0x0000000000017aca
lb: [0x0000000000100000, 0x0000000000218338)
Post relocation: addr: 0x00000000000dcdc0 memsz: 0x0000000000023240 filesz: 0x0000000000017aca
using LZ4
Timestamp - starting LZ4 decompress (ignore for x86): 95781957330
Timestamp - finished LZ4 decompress (ignore for x86): 96179596540
[ 0x000dcdc0, 00100000, 0x00100000) <- ff0721b0
dest 000dcdc0, end 00100000, bouncebuffer bfa57000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 174792 exit 0
Jumping to boot code at 000fcac9(bfcbf000)
Timestamp - selfboot jump: 96249772506
CPU0: stack: 00152000 - 00153000, lowest used address 001529b0, stack used: 1616 bytes
entry = 0x000fcac9
lb_start = 0x00100000
lb_size = 0x00118338
buffer = 0xbfa57000
SeaBIOS (version rel-1.11.1-0-g0551a4b)
BUILD: gcc: (coreboot toolchain v1.50 October 15th, 2017) 6.3.0 binutils: (GNU Binutils) 2.29.1
Attempting to find coreboot table
Found coreboot table forwarder.
Now attempting to find coreboot memory map
SeaBIOS (version rel-1.11.1-0-g0551a4b)
BUILD: gcc: (coreboot toolchain v1.50 October 15th, 2017) 6.3.0 binutils: (GNU Binutils) 2.29.1
Found coreboot cbmem console @ bffd3000
Found mainboard ASUS KGPE-D16
malloc preinit
Relocating init from 0x000de660 to 0xbfc3a840 (size 55072)
malloc init
Found CBFS header at 0xff000238
Add romfile: cbfs master header (size=32)
Add romfile: fallback/romstage (size=177636)
Add romfile: config (size=723)
Add romfile: revision (size=600)
Add romfile: cmos.default (size=256)
Add romfile: cmos_layout.bin (size=3524)
Add romfile: fallback/dsdt.aml (size=9895)
Add romfile: payload_config (size=1593)
Add romfile: payload_revision (size=239)
Add romfile: etc/ps2-keyboard-spinup (size=8)
Add romfile: (size=600)
Add romfile: s3nv (size=65536)
Add romfile: fallback/ramstage (size=89939)
Add romfile: img/coreinfo (size=49298)
Add romfile: img/nvramcui (size=65679)
Add romfile: fallback/payload (size=97026)
Add romfile: img/tint (size=44913)
Add romfile: img/memtest (size=47683)
Add romfile: microcode_amd.bin (size=12684)
Add romfile: microcode_amd_fam15h.bin (size=7876)
Add romfile: (size=16096216)
Add romfile: bootblock (size=2984)
multiboot: eax=0, ebx=0
init ivt
init bda
init bios32
init PMM
init PNPBIOS table
init keyboard
init mouse
init pic
math cp init
PCI probe
PCI device 00:00.0 (vd=1002:5a10 c=0600)
PCI device 00:00.2 (vd=1002:5a23 c=0806)
PCI device 00:02.0 (vd=1002:5a16 c=0604)
PCI device 00:04.0 (vd=1002:5a18 c=0604)
PCI device 00:09.0 (vd=1002:5a1c c=0604)
PCI device 00:0a.0 (vd=1002:5a1d c=0604)
PCI device 00:0b.0 (vd=1002:5a1f c=0604)
PCI device 00:0c.0 (vd=1002:5a20 c=0604)
PCI device 00:0d.0 (vd=1002:5a1e c=0604)
PCI device 00:11.0 (vd=1002:4394 c=0106)
PCI device 00:12.0 (vd=1002:4397 c=0c03)
PCI device 00:12.1 (vd=1002:4398 c=0c03)
PCI device 00:12.2 (vd=1002:4396 c=0c03)
PCI device 00:13.0 (vd=1002:4397 c=0c03)
PCI device 00:13.1 (vd=1002:4398 c=0c03)
PCI device 00:13.2 (vd=1002:4396 c=0c03)
PCI device 00:14.0 (vd=1002:4385 c=0c05)
PCI device 00:14.1 (vd=1002:439c c=0101)
PCI device 00:14.2 (vd=1002:4383 c=0403)
PCI device 00:14.3 (vd=1002:439d c=0601)
PCI device 00:14.4 (vd=1002:4384 c=0604)
PCI device 00:14.5 (vd=1002:4399 c=0c03)
PCI device 00:18.0 (vd=1022:1600 c=0600)
PCI device 00:18.1 (vd=1022:1601 c=0600)
PCI device 00:18.2 (vd=1022:1602 c=0600)
PCI device 00:18.3 (vd=1022:1603 c=0600)
PCI device 00:18.4 (vd=1022:1604 c=0600)
PCI device 00:18.5 (vd=1022:1605 c=0600)
PCI device 00:19.0 (vd=1022:1600 c=0600)
PCI device 00:19.1 (vd=1022:1601 c=0600)
PCI device 00:19.2 (vd=1022:1602 c=0600)
PCI device 00:19.3 (vd=1022:1603 c=0600)
PCI device 00:19.4 (vd=1022:1604 c=0600)
PCI device 00:19.5 (vd=1022:1605 c=0600)
PCI device 00:1a.0 (vd=1022:1600 c=0600)
PCI device 00:1a.1 (vd=1022:1601 c=0600)
PCI device 00:1a.2 (vd=1022:1602 c=0600)
PCI device 00:1a.3 (vd=1022:1603 c=0600)
PCI device 00:1a.4 (vd=1022:1604 c=0600)
PCI device 00:1a.5 (vd=1022:1605 c=0600)
PCI device 00:1b.0 (vd=1022:1600 c=0600)
PCI device 00:1b.1 (vd=1022:1601 c=0600)
PCI device 00:1b.2 (vd=1022:1602 c=0600)
PCI device 00:1b.3 (vd=1022:1603 c=0600)
PCI device 00:1b.4 (vd=1022:1604 c=0600)
PCI device 00:1b.5 (vd=1022:1605 c=0600)
PCI device 03:00.0 (vd=8086:10d3 c=0200)
PCI device 04:00.0 (vd=8086:10d3 c=0200)
PCI device 05:00.0 (vd=1002:67ef c=0300)
PCI device 05:00.1 (vd=1002:aae0 c=0403)
PCI device 07:00.0 (vd=168c:0030 c=0280)
PCI device 08:03.0 (vd=1102:0002 c=0401)
PCI device 08:03.1 (vd=1102:7002 c=0980)
Found 53 PCI devices (max PCI bus is 08)
Relocating coreboot bios tables
Copying SMBIOS entry point from 0xbfc88000 to 0x000f5080
Copying ACPI RSDP from 0xbfc99000 to 0x000f5050
Skipping MPTABLE copy due to large size (1196 bytes)
Copying PIR from 0xbfcbe000 to 0x000f5020
rsdp=0x000f5050
rsdt=0xbfc99030
table(50434146)=0xbfc9b930
pm_tmr_blk=820
Using pmtimer, ioport 0x820
init timer
Scan for VGA option rom
Attempting to init PCI bdf 05:00.0 (vd 1002:67ef)
Attempting to map option rom on dev 05:00.0
Option rom sizing returned f8240000 fffe0000
Inspecting possible rom at 0xf8240000 (vd=1002:67ef bdf=05:00.0)
Copying option rom (size 58880) from 0xf8240000 to 0x000c0000
Checking rom 0x000c0000 (sig aa55 size 115)
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.11.1-0-g0551a4b)
init usb
EHCI init on dev 00:12.2 (regs=0xf840e020)
/bfc37000\ Start thread
EHCI init on dev 00:13.2 (regs=0xf840f020)
/bfc36000\ Start thread
OHCI init on dev 00:12.0 (regs=0xf8408000)
/bfc35000\ Start thread
OHCI init on dev 00:12.1 (regs=0xf8409000)
/bfc34000\ Start thread
OHCI init on dev 00:13.0 (regs=0xf840a000)
/bfc33000\ Start thread
/bfc31000\ Start thread
OHCI init on dev 00:13.1 (regs=0xf840b000)
/bfc30000\ Start thread
/bfc2f000\ Start thread
/bfc2e000\ Start thread
OHCI init on dev 00:14.5 (regs=0xf840c000)
/bfc2d000\ Start thread
/bfc2c000\ Start thread
/bfc2b000\ Start thread
init ps2port
/bfc2a000\ Start thread
|bfc2a000| i8042_flush
|bfc2a000| i8042_command cmd=ad
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=a7
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_flush
|bfc2a000| i8042_command cmd=1aa
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_read
|bfc2a000| i8042 param=55
|bfc2a000| i8042_command cmd=1ab
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_read
|bfc2a000| i8042 param=0
|bfc2a000| Copying data 8 at 0xff02fd38 to 8 at 0xbfc2afd4
/bfc29000\ Start thread
/bfc28000\ Start thread
init floppy drives
init hard drives
ATA controller 1 at 1f0/3f4/0 (irq 14 dev a1)
/bfc27000\ Start thread
|bfc27000| powerup IDE floating
|bfc27000| powerup IDE floating
|bfc27000| ata_detect ata0-0: sc=ff sn=ff dh=ff
|bfc27000| powerup IDE floating
|bfc27000| powerup IDE floating
|bfc27000| ata_detect ata0-1: sc=ff sn=ff dh=ff
\bfc27000/ End thread
/bfc27000\ Start thread
/bfc26000\ Start thread
/bfc25000\ Start thread
/bfc24000\ Start thread
/bfc23000\ Start thread
\bfc23000/ End thread
\bfc29000/ End thread
\bfc2c000/ End thread
\bfc2f000/ End thread
/bfc2f000\ Start thread
\bfc2f000/ End thread
\bfc28000/ End thread
\bfc2b000/ End thread
\bfc2e000/ End thread
\bfc31000/ End thread
ATA controller 2 at 170/374/0 (irq 15 dev a1)
/bfc31000\ Start thread
|bfc31000| powerup iobase=170 st=73
|bfc31000| powerup iobase=170 st=73
|bfc31000| ata_detect ata1-0: sc=73 sn=73 dh=73
|bfc31000| powerup iobase=170 st=73
|bfc31000| powerup iobase=170 st=73
|bfc31000| ata_detect ata1-1: sc=73 sn=73 dh=73
\bfc31000/ End thread
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
/bfc31000\ Start thread
/bfc2f000\ Start thread
/bfc2e000\ Start thread
/bfc2c000\ Start thread
/bfc2b000\ Start thread
/bfc29000\ Start thread
\bfc29000/ End thread
/bfc29000\ Start thread
\bfc29000/ End thread
init ahci
AHCI controller at 00:11.0, iobase 0xf840d000, irq 0
AHCI: cap 0xf722ff85, ports_impl 0x3f
/bfc29000\ Start thread
|bfc29000| AHCI/0: probing
|bfc29000| AHCI/0: link up
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
/bfc28000\ Start thread
/bfc23000\ Start thread
\bfc23000/ End thread
\bfc2f000/ End thread
\bfc27000/ End thread
/bfc2f000\ Start thread
\bfc2f000/ End thread
\bfc2e000/ End thread
\bfc26000/ End thread
/bfc2f000\ Start thread
\bfc2f000/ End thread
\bfc2c000/ End thread
\bfc25000/ End thread
/bfc2f000\ Start thread
\bfc2f000/ End thread
\bfc2b000/ End thread
\bfc24000/ End thread
/bfc2f000\ Start thread
\bfc2f000/ End thread
|bfc37000| ehci_free_pipes 0xbfc38490
/bfc2e000\ Start thread
|bfc2e000| AHCI/1: probing
|bfc2e000| AHCI/1: link up
|bfc29000| Searching bootorder for: /pci at i0cf8/*@11/drive at 0/disk at 0
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
\bfc28000/ End thread
\bfc31000/ End thread
|bfc30000| ohci_free_pipes 0xbfc32f50
|bfc33000| ohci_free_pipes 0xbfc380b0
|bfc34000| ohci_free_pipes 0xbfc38190
|bfc35000| ohci_free_pipes 0xbfc38270
|bfc36000| ehci_free_pipes 0xbfc38380
/bfc2c000\ Start thread
|bfc2c000| AHCI/2: probing
|bfc2c000| AHCI/2: link up
|bfc2e000| AHCI/1: ... finished, status 0x51, ERROR 0x4
|bfc29000| AHCI/0: registering: "DVD/CD [AHCI/0: ASUS DRW-24F1ST a ATAPI-8 DVD/CD]"
|bfc29000| Registering bootable: DVD/CD [AHCI/0: ASUS DRW-24F1ST a ATAPI-8 DVD/CD] (type:3 prio:102 data:f4f70)
\bfc29000/ End thread
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2d000| ohci_free_pipes 0xbfc32d70
\bfc30000/ End thread
\bfc33000/ End thread
\bfc34000/ End thread
\bfc35000/ End thread
\bfc37000/ End thread
/bfc35000\ Start thread
|bfc35000| AHCI/3: probing
|bfc2c000| AHCI/2: ... finished, status 0x51, ERROR 0x4
|bfc2e000| Searching bootorder for: /pci at i0cf8/*@11/drive at 1/disk at 0
|bfc2e000| AHCI/1: supported modes: udma 6, multi-dma 2, pio 4
|bfc2e000| AHCI/1: Set transfer mode to UDMA-6
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
\bfc2d000/ End thread
\bfc36000/ End thread
/bfc36000\ Start thread
|bfc36000| AHCI/4: probing
|bfc35000| AHCI/3: link down
|bfc2c000| Searching bootorder for: /pci at i0cf8/*@11/drive at 2/disk at 0
|bfc2c000| AHCI/2: supported modes: udma 6, multi-dma 2, pio 4
|bfc2c000| AHCI/2: Set transfer mode to UDMA-6
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
/bfc33000\ Start thread
|bfc33000| AHCI/5: probing
|bfc36000| AHCI/4: link down
\bfc35000/ End thread
|bfc2e000| AHCI/1: registering: "AHCI/1: WDC WD20EZRX-00D8PB0 ATA-9 Hard-Disk (1863 GiBytes)"
|bfc2e000| Registering bootable: AHCI/1: WDC WD20EZRX-00D8PB0 ATA-9 Hard-Disk (1863 GiBytes) (type:2 prio:103 data:f4f20)
\bfc2e000/ End thread
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
init megasas
init nvme
init lpt
Found 0 lpt ports
init serial
Found 2 serial ports
Searching bootorder for: /rom at img/memtest
Registering bootable: Payload [memtest] (type:32 prio:9999 data:ff094c40)
Searching bootorder for: /rom at img/tint
Registering bootable: Payload [tint] (type:32 prio:9999 data:ff089c80)
Searching bootorder for: /rom at img/nvramcui
Registering bootable: Payload [nvramcui] (type:32 prio:9999 data:ff062080)
Searching bootorder for: /rom at img/coreinfo
Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ff055fc0)
|bfc33000| AHCI/5: link down
\bfc36000/ End thread
|bfc2c000| AHCI/2: registering: "AHCI/2: WDC WD1002FAEX-00Z3A0 ATA-8 Hard-Disk (931 GiBytes)"
|bfc2c000| Registering bootable: AHCI/2: WDC WD1002FAEX-00Z3A0 ATA-8 Hard-Disk (931 GiBytes) (type:2 prio:103 data:f4ed0)
\bfc2c000/ End thread
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
\bfc33000/ End thread
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| ps2_command aux=0 cmd=1ff
|bfc2a000| i8042 ctr old=30 new=30
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2_sendbyte aux=0 cmd=ff
|bfc2a000| i8042_kbd_write c=255
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 read fe
|bfc2a000| Got ps2 nak (status=51)
|bfc2a000| i8042_command cmd=1060
|bfc2a000| i8042_wait_write
|bfc2a000| i8042_wait_write
|bfc2a000| ps2 command 1ff failed (aux=0)
|bfc2a000| WARNING - Timeout at ps2_keyboard_setup:498!
\bfc2a000/ End thread
All threads complete.
Scan for option roms
Attempting to init PCI bdf 00:00.0 (vd 1002:5a10)
Attempting to map option rom on dev 00:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:00.2 (vd 1002:5a23)
Attempting to map option rom on dev 00:00.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:02.0 (vd 1002:5a16)
Attempting to map option rom on dev 00:02.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:04.0 (vd 1002:5a18)
Attempting to map option rom on dev 00:04.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:09.0 (vd 1002:5a1c)
Attempting to map option rom on dev 00:09.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:0a.0 (vd 1002:5a1d)
Attempting to map option rom on dev 00:0a.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:0b.0 (vd 1002:5a1f)
Attempting to map option rom on dev 00:0b.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:0c.0 (vd 1002:5a20)
Attempting to map option rom on dev 00:0c.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:0d.0 (vd 1002:5a1e)
Attempting to map option rom on dev 00:0d.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:14.0 (vd 1002:4385)
Attempting to map option rom on dev 00:14.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.1 (vd 1002:439c)
Attempting to map option rom on dev 00:14.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.2 (vd 1002:4383)
Attempting to map option rom on dev 00:14.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.3 (vd 1002:439d)
Attempting to map option rom on dev 00:14.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.4 (vd 1002:4384)
Attempting to map option rom on dev 00:14.4
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:18.0 (vd 1022:1600)
Attempting to map option rom on dev 00:18.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.1 (vd 1022:1601)
Attempting to map option rom on dev 00:18.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.2 (vd 1022:1602)
Attempting to map option rom on dev 00:18.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.3 (vd 1022:1603)
Attempting to map option rom on dev 00:18.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.4 (vd 1022:1604)
Attempting to map option rom on dev 00:18.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.5 (vd 1022:1605)
Attempting to map option rom on dev 00:18.5
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.0 (vd 1022:1600)
Attempting to map option rom on dev 00:19.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.1 (vd 1022:1601)
Attempting to map option rom on dev 00:19.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.2 (vd 1022:1602)
Attempting to map option rom on dev 00:19.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.3 (vd 1022:1603)
Attempting to map option rom on dev 00:19.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.4 (vd 1022:1604)
Attempting to map option rom on dev 00:19.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.5 (vd 1022:1605)
Attempting to map option rom on dev 00:19.5
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1a.0 (vd 1022:1600)
Attempting to map option rom on dev 00:1a.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1a.1 (vd 1022:1601)
Attempting to map option rom on dev 00:1a.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1a.2 (vd 1022:1602)
Attempting to map option rom on dev 00:1a.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1a.3 (vd 1022:1603)
Attempting to map option rom on dev 00:1a.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1a.4 (vd 1022:1604)
Attempting to map option rom on dev 00:1a.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1a.5 (vd 1022:1605)
Attempting to map option rom on dev 00:1a.5
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1b.0 (vd 1022:1600)
Attempting to map option rom on dev 00:1b.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1b.1 (vd 1022:1601)
Attempting to map option rom on dev 00:1b.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1b.2 (vd 1022:1602)
Attempting to map option rom on dev 00:1b.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1b.3 (vd 1022:1603)
Attempting to map option rom on dev 00:1b.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1b.4 (vd 1022:1604)
Attempting to map option rom on dev 00:1b.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1b.5 (vd 1022:1605)
Attempting to map option rom on dev 00:1b.5
Option rom sizing returned 0 0
Attempting to init PCI bdf 03:00.0 (vd 8086:10d3)
Attempting to map option rom on dev 03:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 04:00.0 (vd 8086:10d3)
Attempting to map option rom on dev 04:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 05:00.1 (vd 1002:aae0)
Attempting to map option rom on dev 05:00.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 07:00.0 (vd 168c:0030)
Attempting to map option rom on dev 07:00.0
Option rom sizing returned f8320000 ffff0000
Inspecting possible rom at 0xf8320000 (vd=168c:0030 bdf=07:00.0)
No option rom signature (got 0)
Attempting to init PCI bdf 08:03.0 (vd 1102:0002)
Attempting to map option rom on dev 08:03.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:03.1 (vd 1102:7002)
Attempting to map option rom on dev 08:03.1
Option rom sizing returned 0 0
Press ESC for boot menu.
Checking for bootsplash
Searching bootorder for: HALT
Mapping cd drive 0x000f4f70
Mapping hd drive 0x000f4f20 to 0
drive 0x000f4f20: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=3907029168
Mapping hd drive 0x000f4ed0 to 1
drive 0x000f4ed0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
finalize PMM
malloc finalize
Space available for UMB: ce800-ea800, f48a0-f4ea0
Returned 253952 bytes of ZoneHigh
e820 map has 10 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 00000000bfc86000 = 1 RAM
4: 00000000bfc86000 - 00000000d0000000 = 2 RESERVED
5: 00000000f8400000 - 00000000f8404000 = 2 RESERVED
6: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
7: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
8: 00000000fed00000 - 00000000fed01000 = 2 RESERVED
9: 0000000100000000 - 0000000840000000 = 1 RAM
Jump to int19
enter handle_19:
NULL
Booting from DVD/CD...
scsi_is_ready (drive=0x000f4f70)
AHCI/0: ... finished, status 0x51, ERROR 0x60
AHCI/0: ... finished, status 0x51, ERROR 0x20
Device reports MEDIUM NOT PRESENT
scsi_is_ready returned -1
AHCI/0: ... finished, status 0x51, ERROR 0x20
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
handle_hwpic1 irq=1
-------------- next part --------------
#
# Automatically generated file; DO NOT EDIT.
# SeaBIOS Configuration
#
#
# General Features
#
CONFIG_COREBOOT=y
# CONFIG_QEMU is not set
# CONFIG_CSM is not set
# CONFIG_QEMU_HARDWARE is not set
CONFIG_THREADS=y
CONFIG_RELOCATE_INIT=y
CONFIG_BOOTMENU=y
CONFIG_BOOTSPLASH=y
CONFIG_BOOTORDER=y
CONFIG_COREBOOT_FLASH=y
CONFIG_LZMA=y
CONFIG_CBFS_LOCATION=0
CONFIG_MULTIBOOT=y
CONFIG_ENTRY_EXTRASTACK=y
CONFIG_MALLOC_UPPERMEMORY=y
CONFIG_ROM_SIZE=0
#
# Hardware support
#
CONFIG_ATA=y
# CONFIG_ATA_DMA is not set
# CONFIG_ATA_PIO32 is not set
CONFIG_AHCI=y
CONFIG_SDCARD=y
CONFIG_MEGASAS=y
CONFIG_FLOPPY=y
CONFIG_FLASH_FLOPPY=y
CONFIG_NVME=y
CONFIG_PS2PORT=y
CONFIG_USB=y
CONFIG_USB_UHCI=y
CONFIG_USB_OHCI=y
CONFIG_USB_EHCI=y
CONFIG_USB_XHCI=y
CONFIG_USB_MSC=y
CONFIG_USB_UAS=y
CONFIG_USB_HUB=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_MOUSE=y
CONFIG_SERIAL=y
CONFIG_SERCON=y
CONFIG_LPT=y
CONFIG_RTC_TIMER=y
CONFIG_HARDWARE_IRQ=y
CONFIG_PMTIMER=y
CONFIG_TSC_TIMER=y
#
# BIOS interfaces
#
CONFIG_DRIVES=y
CONFIG_CDROM_BOOT=y
CONFIG_CDROM_EMU=y
CONFIG_PCIBIOS=y
CONFIG_APMBIOS=y
CONFIG_PNPBIOS=y
CONFIG_OPTIONROMS=y
CONFIG_PMM=y
CONFIG_BOOT=y
CONFIG_KEYBOARD=y
CONFIG_KBD_CALL_INT15_4F=y
CONFIG_MOUSE=y
CONFIG_S3_RESUME=y
CONFIG_VGAHOOKS=y
# CONFIG_DISABLE_A20 is not set
CONFIG_TCGBIOS=y
#
# VGA ROM
#
CONFIG_NO_VGABIOS=y
# CONFIG_VGA_GEODEGX2 is not set
# CONFIG_VGA_GEODELX is not set
# CONFIG_VGA_COREBOOT is not set
# CONFIG_BUILD_VGABIOS is not set
CONFIG_VGA_EXTRA_STACK_SIZE=512
#
# Debugging
#
CONFIG_DEBUG_LEVEL=7
CONFIG_DEBUG_SERIAL=y
CONFIG_DEBUG_SERIAL_PORT=0x3f8
CONFIG_DEBUG_COREBOOT=y
-------------- next part --------------
# This image was built using coreboot 4.8.1-6794ce02d45273427c1c6675950c8468380c040a
CONFIG_USE_OPTION_TABLE=y
CONFIG_TIMESTAMPS_ON_CONSOLE=y
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_ASUS=y
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_BOARD_ASUS_KGPE_D16=y
# CONFIG_POST_IO is not set
# CONFIG_POST_DEVICE is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
CONFIG_SEABIOS_PS2_TIMEOUT=3000
CONFIG_BOOTBLOCK_NORMAL=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
# CONFIG_SEABIOS_VGA_COREBOOT is not set
CONFIG_SEABIOS_DEBUG_LEVEL=7
CONFIG_COMPRESSED_PAYLOAD_LZ4=y
CONFIG_COREINFO_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
-------------- next part --------------
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