[coreboot] Why coreboot for riscv does not support multi-core?

Jonathan Neuschäfer j.neuschaefer at gmx.net
Fri May 18 12:19:31 CEST 2018


On Fri, May 18, 2018 at 11:46:54AM +0800, 王翔 wrote:
[...]
> Is coreboot's payload a bootloader running in m-mode ?
> If not, how does the SBI interrupt service be implemented ?

Previously, coreboot implemented the SBI, and launched the payload in
S-mode. The SBI implementation implemented the old version of the SBI
(a page mapped at a certain virtual address), so I removed it in commit
3ca8b598ed ("arch/riscv: Remove the current SBI implementation")[3].
The payload is still launched in S-mode, because noone has changed that.

So the new version of the SBI needs to be implemented.

There are two options:

1. Implement the new SBI in coreboot, and keep launching the payload in
   S-mode.

2. Implement the new SBI in a payload or some other kind of module, akin
   to ARM Trusted Firmware[1] or bbl[2]; Launch the code that implements
   the SBI in M-mode.


Jonathan Neuschäfer

[1]: https://github.com/ARM-software/arm-trusted-firmware/
[2]: https://github.com/riscv/riscv-pk/tree/master/bbl
[3]: https://review.coreboot.org/cgit/coreboot.git/commit/?h=3ca8b598ed4ea16fd55d0d8108749c1da537a036
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