[coreboot] Building coreboot for Apollo Lake: missing 'IFWI' region
Hal Martin
hal.martin at gmail.com
Fri May 11 08:32:46 CEST 2018
Hi all,
I am trying to build coreboot for an Apollo Lake platform. I've read the
coreboot presentation on Apollo Lake, and some of the threads about the
IFWI on the coreboot mailing list:
https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf
https://mail.coreboot.org/pipermail/coreboot/2017-November/085482.html
https://mail.coreboot.org/pipermail/coreboot/2017-September/085217.html
After reading this and digesting the information for a week, I'm still no
closer to understanding how the build process is supposed to work.
I have extracted the descriptor from the SPI image, and put the entire 16MB
image in the 3rdparty directory. When I try to build coreboot, I'm getting
the following error:
Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.
Image does not contain sub-partition OBBP(6).
Sub-partition IBBP(4) entry IBBL replaced from file
build/cbfs/fallback/bootblock.bin.
Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.
E: Image is missing 'IFWI' region
E: The image will be left unmodified.
src/soc/intel/apollolake/Makefile.inc:137: recipe for target 'files_added'
failed
make: *** [files_added] Error 1
Attached is the output of ifdtool and ifwitool for the SPI dump of the
vendor firmware for platform I'm working on.
A few interesting observations (from my perspective):
- There doesn't seem to be an OBBP in this image.
- My ifwitool output seems to match the output of others (e.g.
https://mail.coreboot.org/pipermail/coreboot/2017-September/085210.html )
- This platform (CompuLab Fitlet 2) only has SPI flash, no EMMC. My
understanding is that IFWI is the same whether it's on EMMC or SPI.
Some open questions I have:
- Is it possible to build a flashable image using only coreboot and a dump
of the vendor firmware, or does one need to use the Intel FSP and FIT tools
and some "stitching" to get a flashable image with a coreboot payload?
- Is there any public documentation available describing the FSP 2.0/IFWI
flash layout?
- Is it possible to obtain FIT for Apollo Lake without having an NDA or
corporate account with Intel? It seems that absolutely everything about
Apollo Lake is classified as "confidential" on Intel's website:
https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/apollo-lake/technical-library.html?grouping=rdc%20Content%20Types
Can anyone who was working on an FSP 2.0 platform (e.g. Cameron Craig, Paul
Penz, Morris) follow up on how they managed to build a flashable image?
Thanks,
Hal
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20180511/5ba4a254/attachment-0001.html>
-------------- next part --------------
File /tmp/fitlet2_stock.bin is 16777216 bytes
FLMAP0: 0x00040003
NR: 0
FRBA: 0x40
NC: 1
FCBA: 0x30
FLMAP1: 0x13100208
ISL: 0x13
FPSBA: 0x100
NM: 2
FMBA: 0x80
FLMAP2: 0x00000000
PSL: 0x0000
FMSBA: 0x0
FLUMAP1: 0x000004df
Intel ME VSCC Table Length (VTL): 4
Intel ME VSCC Table Base Address (VTBA): 0x000df0
ME VSCC table:
JID0: 0x0000471f
SPI Componend Device ID 1: 0x00
SPI Componend Device ID 0: 0x47
SPI Componend Vendor ID: 0x1f
VSCC0: 0x20152015
Lower Erase Opcode: 0x20
Lower Write Enable on Write Status: 0x06
Lower Write Status Required: No
Lower Write Granularity: 64 bytes
Lower Block / Sector Erase Size: 4KB
Upper Erase Opcode: 0x20
Upper Write Enable on Write Status: 0x06
Upper Write Status Required: No
Upper Write Granularity: 64 bytes
Upper Block / Sector Erase Size: 4KB
JID1: 0x0018421f
SPI Componend Device ID 1: 0x18
SPI Componend Device ID 0: 0x42
SPI Componend Vendor ID: 0x1f
VSCC1: 0x20252025
Lower Erase Opcode: 0x20
Lower Write Enable on Write Status: 0x50
Lower Write Status Required: No
Lower Write Granularity: 64 bytes
Lower Block / Sector Erase Size: 4KB
Upper Erase Opcode: 0x20
Upper Write Enable on Write Status: 0x50
Upper Write Status Required: No
Upper Write Granularity: 64 bytes
Upper Block / Sector Erase Size: 4KB
OEM Section:
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Found Region Section
FLREG0: 0x00000000
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1: 0x0efe0001
Flash Region 1 (BIOS): 00001000 - 00efefff
FLREG2: 0x00007fff
Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
FLREG3: 0x00007fff
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4: 0x00007fff
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG5: 0x0ffe0eff
Flash Region 5 (Reserved): 00eff000 - 00ffefff
FLREG6: 0x00007fff
Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
FLREG7: 0x00007fff
Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
FLREG8: 0x00007fff
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
Found Component Section
FLCOMP 0x36dc02f5
Dual Output Fast Read Support: not supported
Read ID/Read Status Clock Frequency: 17MHz
Write/Erase Clock Frequency: 17MHz
Fast Read Clock Frequency: 17MHz
Fast Read Support: supported
Read Clock Frequency: 17MHz
Component 2 Density: UNUSED
Component 1 Density: 16MB
FLILL 0xad604221
Invalid Instruction 3: 0xad
Invalid Instruction 2: 0x60
Invalid Instruction 1: 0x42
Invalid Instruction 0: 0x21
FLPB 0xc7c4b9b7
Flash Partition Boundary Address: 0x9b7000
Found PCH Strap Section
PCHSTRP0: 0x000610a1
PCHSTRP1: 0x00ff0000
PCHSTRP2: 0xc8000002
PCHSTRP3: 0x00000665
PCHSTRP4: 0x00000000
PCHSTRP5: 0x00600304
PCHSTRP6: 0x00100000
PCHSTRP7: 0x00000032
PCHSTRP8: 0x00005007
PCHSTRP9: 0x00000010
PCHSTRP10: 0x00100000
PCHSTRP11: 0x00041004
PCHSTRP12: 0x00004000
PCHSTRP13: 0x00000000
PCHSTRP14: 0x00004000
PCHSTRP15: 0x00000000
PCHSTRP16: 0x00000004
PCHSTRP17: 0x00000000
Found Master Section
FLMSTR1: 0x00200300 (Host CPU/BIOS)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: enabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: disabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
FLMSTR2: 0x02402700 (Intel ME)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: enabled
Host CPU/BIOS Region Write Access: disabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: enabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
FLMSTR3: 0x00000000 (GbE)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: disabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: disabled
Host CPU/BIOS Region Read Access: disabled
Flash Descriptor Read Access: disabled
FLMSTR5: 0x00000000 (EC)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: disabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: disabled
Host CPU/BIOS Region Read Access: disabled
Flash Descriptor Read Access: disabled
Found Processor Strap Section
????: 0xffffffff
????: 0xffffffff
????: 0xffffffff
????: 0xffffffff
????: 0x0ff0a55a
????: 0x00040003
????: 0x13100208
????: 0x00000000
File /tmp/fitlet2_stock.bin is 16777216 bytes
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
Flash Region 1 (BIOS): 00001000 - 00efefff
Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
Flash Region 5 (Reserved): 00eff000 - 00ffefff
Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
-------------- next part --------------
Header BPDT
Signature 0x000055aa
Descriptor count 13
BPDT Version 1
XOR checksum 0x0
IFWI Version 0x0
FIT Tool Version 0x8ae003200010003
BPDT entries
Entry # Sub-Partition Name Type Flags Offset Size File Offset
=========================================================================================================================================================================================================
1 DLMP CSE_IDLM 9 0x00000000 0x0 0x0 0x0
2 IFP_OVERRIDE IFP_OVERRIDE 10 0x00000000 0x200 0x10 0x200
3 S_BPDT S-BPDT 5 0x00000000 0x146000 0x141000 0x146000
4 RBEP CSE_RBE 1 0x00000000 0x5000 0xa000 0x5000
5 UFS_PHY UFS Phy 12 0x00000000 0x0 0x0 0x0
6 UFS_GPP UFS GPP 13 0x00000000 0x0 0x0 0x0
7 FTPR CSE_BUP 2 0x00000000 0x1f000 0x61000 0x1f000
8 UEP UEP 17 0x00000000 0x210 0x108 0x210
9 SMIP SMIP 0 0x00000000 0x1000 0x4000 0x1000
10 PMCP PMC firmware 14 0x00000000 0xf000 0x10000 0xf000
11 UCOD Microcode 3 0x00000000 0x80000 0xd000 0x80000
12 IBBP Bootblock 4 0x00000000 0x8d000 0xb7000 0x8d000
13 DEBUG_TOKENS Debug Tokens 11 0x00000000 0x144000 0x2000 0x144000
=========================================================================================================================================================================================================
Header S-BPDT
Signature 0x000055aa
Descriptor count 3
BPDT Version 1
XOR checksum 0x0
IFWI Version 0x0
FIT Tool Version 0x8ae003200010003
S-BPDT entries
Entry # Sub-Partition Name Type Flags Offset Size File Offset
=========================================================================================================================================================================================================
1 ISHP ISH 8 0x00000000 0x147000 0x40000 0x147000
2 NFTP CSE_MAIN 7 0x00000000 0x187000 0xfe000 0x187000
3 IUNP IUNIT 15 0x00000000 0x285000 0x2000 0x285000
=========================================================================================================================================================================================================
More information about the coreboot
mailing list