[coreboot] Minnowboard

[Piotr Król]

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On 03/22/2018 10:27 AM, Daniel Wagner wrote:
> Hi Piotr,

Hi Daniel,

(...)

> 
> Is the TXE code also part of the rom? I wonder why it is not
> showing up in the ifdtool output.

It shows under position of ME. ME for Bay Trail is called TXE.

(...)

>> This will give you layout file similar to: 00000000:00000fff fd 
>> 00400000:007fffff bios 00001000:003fffff me 00000000:00000fff
>> gbe
> I got this as well. Zoran just told me offline that fd and gbe
> seems to overlap. He also told me that the layout should be fd,
> gbe, me and finally bios. Is the ifdtool output correct?

I also wonder about that. IMO there can be 2 things - incorrect
parsing of flash descriptor by ifdtool or incorrect values in flash
descriptor. This may be because this firmware doesn't have GbE
firmware. I wondered what will happen if we apply different
permissions to fd and gbe.

If you look at addresses bios is at the end. At least this layout
works. How to interpret overlapping regions I don't know.

> 
>> Then copy build/coreboot.rom and layout file to your RPi and
>> flash:
>> 
>> (rpi) $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32000
>> -l \ layout -i bios -w /tmp/coreboot.rom
>> 
>> Our container have default FSP from GitHub which is not the most 
>> recent one. Latest you can obtain only through Intel RDC portal.
> 
> I suppose the one from GitHub is good enough though? I don't have
> an RDC portal account.

Yes. But if you would like to complain to Intel for performance
related stuff they will say "please use recent one" and then you can
complain on correct one :)

Best Regards,
- -- 
Piotr Król
Embedded Systems Consultant
http://3mdeb.com | @3mdeb_com
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