[coreboot] ARM Veyron Speedy - Replacing 11.6 inch display for 15 inch

[Mark Wylde]

Thanks Nico for taking your valuable time to answer my questions. I really appreciate it, and knowing that it should be possible makes me feel better about continuing the project. 

I've ordered another display that has better matching specifications. I'll reply here to let others know if it works or not although I agree this is probably not a coreboot issue.

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐

On March 4, 2018 2:10 PM, Nico Huber <nico.h at gmx.de> wrote:

> ​​
> 
> Hello Mark,
> 
> On 04.03.2018 11:45, Mark Wylde wrote:
> 
> > The ASUS C201 comes with an 11.6inch EDP display. I was wondering if you
> > 
> > could simply swap it for a 15'' EDP display. I tried it, but as expected
> > 
> > it didn't work, however the backlight came on and I had the following
> > 
> > logs:
> 
> snip
> 
> > Configuring PLL at ff760040 with NF = 1346, NR = 59 and NO = 4 (VCO = 547525KHz, output = 136881KHz)
> > 
> > requested signal parameters: lane 0 voltage 0.6V pre_emph 0dB
> > 
> > requested signal parameters: lane 1 voltage 0.6V pre_emph 0dB
> > 
> > using signal parameters: voltage 0.6V pre_emph 0dB
> > 
> > requested signal parameters: lane 0 voltage 0.8V pre_emph 0dB
> > 
> > requested signal parameters: lane 1 voltage 0.8V pre_emph 0dB
> > 
> > using signal parameters: voltage 0.8V pre_emph 0dB
> > 
> > requested signal parameters: lane 0 voltage 1.2V pre_emph 0dB
> > 
> > requested signal parameters: lane 1 voltage 1.2V pre_emph 0dB
> > 
> > using signal parameters: voltage 1.2V pre_emph 0dB
> > 
> > clock recovery reached max voltage
> > 
> > clock recovery failed
> > 
> > link train failed!
> > 
> > edp enable err
> > 
> > 
> > -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> 
> This is the DP training sequence. DP has two communication channels to
> 
> the display, 1. up to 4 data lanes for the picture data operating at GHz
> 
> rates that have to be trained, 2. an AUX channel operating at MHz speed
> 
> that is supposed to just work (it does here).
> 
> Basically, your display keeps telling through the AUX channel "I can't
> 
> hear you, speak louder!". Until the highest voltage is reached.
> 
> > It looks to me (as a complete noob) that the display
> > 
> > (http://www.yslcd.com.tw/docs/product/N156HGE-EAB.pdf) needs around 3.3
> > 
> > volts.
> 
> The 3.3V are the power supply voltage for the display. This is (usually)
> 
> not configurable, but if it were, then likely not from coreboot but the
> 
> EC. You should make sure that the electrical characteristics (4.3.1 in
> 
> that datasheet) match those of the old display. If they don't, all bets
> 
> are off.
> 
> > Looking at the code, it seems the ./src/soc/rockchip/common/edp.c
> > 
> > handles this part of the booting process. Line 38 seems to imply the
> > 
> > maximum voltage is 1.2v.
> 
> This, however, is about the i/o voltage for the data lanes, and unre-
> 
> lated to the 3.3V.
> 
> > \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- static
> > 
> > const char *voltage_names\[\] = { "0.4V", "0.6V", "0.8V", "1.2V" };
> > 
> > 
> > ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> > 
> > Is there a reason this is the maximum? Unfortunately there doesn't seem
> > 
> > to be much information on the specifications of the C201, I guess as
> > 
> > it's not really an open machine. Maybe the motherboard can only handle
> > 
> > that voltage?
> 
> It's the maximum specified for DP.
> 
> > I'm extremely new to coreboot, and to be honest not even sure the C201
> > 
> > can even handle a 15'' display. Does anyone know if I'm on the right
> > 
> > track, or if this is a pointless exercise?
> 
> Your problem has nothing to do with coreboot, I guess. Though, that log
> 
> is useful for debugging of course. If the electrical characteristics
> 
> match those of the old display (i.e. we can expect that the new display
> 
> is generally operational), it might be a signal integrity problem, or
> 
> something is not connected correctly at all...
> 
> The C201 generally shouldn't care about the size or the resolution of
> 
> the display. At the eDP level, everything should be compatible. The
> 
> power supply for the display, OTOH, is not part of the eDP specification
> 
> and just has to match what the board supplies (or you have to build your
> 
> own power supply).
> 
> Hope that helps,
> 
> Nico
> 
> 
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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