[coreboot] how does FSP play its role in Haswell/Broadwell/Skylake

[Matt DeVillier]

Haswell and Broadwell don't use FSP, they use the MRC blob for RAM init.
For Haswell, coreboot does all of the silicon init as well; for Broadwell,
coreboot does most of the silicon init, and some bits are handled by
another blob (refcode.elf).  Skylake uses FSP (1.1 or 2.0, depending on the
board in question) for both RAM and silicon init.

cheers,
Matt

On Sun, Mar 4, 2018 at 11:12 PM, Zheng Bao <fishbaoz at hotmail.com> wrote:

> Hi,
>
> how does FSP play its role in Haswell/Broadwell/Skylake?
>
>
> Take the Broadwell as the example, which I ported coreboot successfully.
>
>
> I use the mrc.bin and vboot.bin from Chromebook BIOS image.
>
> I use the ME tool, fitc, to add the IFD to the BIOS image.
>
> The final image works well and boots linux.
>
>
> But where is FSP? Or which is FSP?
>
>
> Zheng
>
> --
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>
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