[coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board
j.neuschaefer at gmx.net
Sun Jun 24 20:46:32 CEST 2018
On Fri, Jun 22, 2018 at 01:01:04PM +0200, Jonathan Neuschäfer wrote:
> Section 20.3 describes the initialization sequence for the DRAM
> controller, but leaves out the values for the register for "memory
> timing settings, PAD mode configuration, initialization, and training."
> It says: "Please contact SiFive directly to determine the complete
> register settings for your application."
> I will ask on the forum.
"While we’d love to provide you with this information, we believe we
cannot. However, we can’t prevent anyone from disassembling the fsbl and
copying the values sent to the blackbox DDR register map."
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