[coreboot] Bayley Bay FSP-based CRB
nico.h at gmx.de
Thu Jun 21 10:12:12 CEST 2018
On 18.06.2018 05:24, Zvi Vered wrote:
> 1. The size of CBFS is: 0x200000. Is it a fix size or should I change it
> according to my board (which is also bay trail) ?
on Intel platforms, the SPI flash is shared with other chipset compo-
nents. The CBFS_SIZE should be at most the size of the "BIOS" region
of the flash.
> 3. In this board default configuration, "Configure defaults for the Intel
> FSP package" is not selected. Is it possible that this board does not use
> Intel FSP at all ?
> Under "Generic Drivers", "Use Intel firmware Support Package' is also not
FSP is mandatory for a bootable image. It is not enabled by default
because Intel does not (always) publish the matching binaries, but our
build tests require the defaults to build. This leaves us with unfor-
tunate default settings for all Intel FSP platforms that will never
boot. If you think that is a bad idea (I do) please let Intel know that
you are interested in working defaults and that it requires them to
publish all the binaries that are integrated into coreboot.
> 4. Under "chipset", there is no option to set "Super I/O". Can you please
> tell why ?
Our config options do not allow board specific changes. For such
settings, each board has it's own directory and Kconfig file
> 5. I noticed that the minimum ROM size is 2MB. If I set 4MB, the size of
> coreboot.rom is also 4MB.
That is correct, but keep in mind that the flash is shared. The
resulting coreboot.rom might not contain everything that is required
to boot. So it is best advised to only flash the "BIOS" region of
Hope that helps,
More information about the coreboot