[coreboot] Missing PCIe devices

[Kyösti Mälkki]

Hi

On Sat, Jan 13, 2018 at 8:51 PM, Hal Martin <hal.martin at gmail.com> wrote:
> Hi all,
>
> Is there any documentation around describing how coreboot scans for PCI
> Express buses and devices?

Don't know of one. It's a recursive walk of the PCI tree, with the
assigned bus number incremented for every detected PCI bridge. How
vendor firmware does assignment may be different.

> I have an expansion module for the Intense PC I'd like to get working with
> Coreboot. The expansion module adds 4 Intel Gigabit Ethernet interfaces
> (82574L) via PCI Express 4 PCIe ports. All interfaces are on the same
> physical FACE module.
>
> In the vendor firmware, all four cards are properly detected:
> 01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
> 03:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
> 06:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
> 07:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
>
> But in coreboot, only the first two cards are detected:
> 01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
> 03:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> Connection
>
> It seems from the coreboot uart output that coreboot isn't scanning PCIe
> buses 6 & 7. Looking at pci_scan_bus in src/device/pci_device.c it seems
> coreboot should be recursively scanning PCI bridges for any devices behind
> them. The lspci output from the vendor firmware and coreboot lists the same
> number of PCI bridges:
> 00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor
> PCI Express Root Port (rev 09)
> 00:01.1 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor
> PCI Express Root Port (rev 09)
>

Can you send 'lspci -tnv' output and 'sudo lspci -xxxx' from vendor
firmware boot. Same for coreboot and perhaps the complete log. There
are more PCIe root ports on device 0:1c.0, some of those you have
marked disabled in devicetree.cb.

> From the boot logs, it seems that coreboot stops scanning after PCI bus 05:

Default limit should be 63 for sandy/ivy and you could increase it to
127 or 255.

Kyösti