[coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

[Nico Huber]

Hi Nicola,

On 01.02.2018 09:48, Nicola Corna wrote:
> Hi Nico,
> 
> any update on this?

omg sorry, looks like I completely forgot about it. And even worse, now
that I looked into it, it seems to be impossible to do like I suggested.
Because bd82x6x/finalize.c is run in SMM and we don't have the device-
tree there. I guess we have to prepare the register contents and only
lock them in the finalization function. Don't have time to test it, but
[1] might work.

Nico

[1] https://review.coreboot.org/#/c/coreboot/+/23587

> 
> Best,
> Nicola
> 
> September 5, 2017 11:01 AM, "Nico Huber" <nico.h at gmx.de> wrote:
> 
>> On 04.09.2017 19:31, Nicola Corna wrote:
>>
>>> September 3, 2017 12:24 AM, "Nico Huber" <nico.h at gmx.de> wrote:
>>>
>>>> TLDR; it would be a lot slower.
>>>>
>>>> Alas, there is no usual byte-program mode. Most chips do a 256B page
>>>> program which uses op code 0x02 too. For the SST25VF032B it's really a
>>>> 1B program. If you use that instead of the AAI write, you get lots of
>>>> overhead (6B total, if I'm not mistaken, instead of ~1.5B per actual
>>>> written byte + twice the polling for write-in-progress).
>>>>
>>>> Nico
>>>
>>> Thank you.
>>>
>>> I've noticed that some boards have already an extra "finalize", which overrides
>>> the default opmenu and optype (see mb/siemens/mc_bdx1/mainboard.c):
>>
>> AFAICS, these boards use very different code paths with different inter-
>> faces to override the op menu configuration.
>>
>>> should I
>>> copy that implementation or add the configurations in the device tree and modify
>>> every sb/intel/*/pch.h (as you suggested before)?
>>
>> I didn't mean to suggest modifying every pch.h, but only sb/intel/
>> bd82x6x/finalize.c (the pch.h should stay intact to give defaults).
>> It's probably easier if I put my idea into a patch for discussion.
>> Stay tuned.
>>
>> Nico
>>
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>