[coreboot] AMD fam10 relocatable ramstage
arthur at aheymans.xyz
Sun Dec 9 19:06:12 CET 2018
I have been playing around with the AMD fam10 codebase as of late.
It is quite different from Intel hardware is that AMD hardware starts up
other AP cores whereas on Intel hardware typically only the BSP runs code.
As far as I can tell the AP's are started early on. They then start
running from the reset vector. The code then updates their microcode
and sets a 'reasonable' TOP_MEM MTRR such that when starting the APs
later on during the ramstage, it won't result in any problems given that the
stack will be in that 'reasonable' range (below CONFIG_RAMTOP). After that,
they are put to rest and the BSP will be doing the rest of the things
during the romstage (raminit for instance).
Now the cbmem_top depends on the value the BSP set's in TOP_MEM, but
unless the AP's have their own TOP_MEM (not shared MTRR) synced with the
BSP. This syncing only happens during the AP init.
To implement relocatable ramstage this syncing needs to happen earlier,
preferable during the romstage...
At the moment with relocatable ramstage enabled it hangs when starting
the APs as it puts their stack somewhere in CBMEM well above the
'reasonable' default value of TOP_MEM which is CONFIG_RAMTOP.
Now my questions:
- Is this analysis correct?
- If so, how to sync TOP_MEM in romstage (is there already an example of
an implementation somewhere?), is there an easy way to run code on
all AP's during the romstage?
- Are workarounds possible/better? like figuring out TOP_MEM saving it
nvram and resetting and programming that value on AP's
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