[coreboot] Testing asked, implementing POSTCAR stage
arthur at aheymans.xyz
Thu Dec 6 01:34:07 CET 2018
I'm trying to implement a few features on x86 platforms to improve
coreboot. Currently I'm focusing on unifying the bootflow of x86
platforms a little better. An important aspect of that is to make sure
program boundaries within stages are respected, which is mostly an issue
when romstage destroys the stack+environment in which it is running.
Currently many platforms work around it by having code to fetch the
global variables which are either still in the CAR (before CAR tear
down) or somewhere relocated in cbmem after cbmem has been set up.
A better solution is to have CAR being torn down in a separate stage,
which means that romstage can always access global variables where the
linker initially puts them. We call this stage postcar stage.
I have an implementation ready for the following platforms:
* CPU_AMD_MODEL_10XXX or in mainboard terms:
It would be great if the following patches could be tested (i.e. does it
preferably on a board on which ACPI S3 resume is implemented (select HAVE_ACPI_RESUME).
* NORTHBRIDGE_VIA_VX900 on the VIA EPIA-M850 board
The only remaining targets that need to be addressed before the special
logic for CAR globals can be dropped are FSP1.0 platforms and geode_lx.
geode_lx still has to implement EARLY_CBMEM (requirement for 4.7 and 4.9 is
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