[coreboot] BayTrail LPC configuration (was: Re: Configuration for Apollo Lake FSP (Github/MR5))
realman.bau at gmail.com
Tue Dec 4 20:23:10 CET 2018
Maybe the problem is that SERIRQ are disabled? Why is it necessary to use
SERIRQ for BayTrail when connecting superio to lpc bus?
From: Nico Huber
Sent: Wednesday, November 21, 2018 12:38 AM
To: Alexey Borovikov
Cc: coreboot at coreboot.org
Subject: BayTrail LPC configuration (was: Re: Configuration for Apollo Lake
On 11/20/18 7:13 PM, Alexey Borovikov wrote:
> Is there an external superio on your board?
yes, kind of. There's an FPGA attached to the LPC bus that exposes UARTs
among some other interfaces.
> At the moment I am trying to solve the problem of initializing the
> external superio chip for the SOC Baytrail processor, but so far without
I don't know the Bay Trail SoC. But my most common advice might help
here: Do all pin/pad configuration (e.g. GPIOs) first. This seems to
affect even very common connections on Intel's Atom SoCs. What I just
learned during the past few days: LPC isn't the default configuration
on Apollo Lake, and the same seems to be true for Bay Trail.
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