[coreboot] Problem about GPIO

[王翔]

I try to porting coreboot to msi's Motherboard(H110 chipset).  
I read GPIO config from PCR config space under linux.
But the value I got was very strange.


eg:
//DW0 and DW1 cannot be 0xffffffff according to the data sheet
PIN:GPP_C6  DW1,DW0:ffffffff,ffffffff FUNC:(null) PULL:NATIVE RESET:RSMRST TX_DISABLE:1 RX_DISABLE:1 RXINV:INVERT TRIG:EDGE_BOTH   ROUTE:NMI SMI SCI IOACPI
PIN:GPP_C7  DW1,DW0:ffffffff,ffffffff FUNC:(null) PULL:NATIVE RESET:RSMRST TX_DISABLE:1 RX_DISABLE:1 RXINV:INVERT TRIG:EDGE_BOTH   ROUTE:NMI SMI SCI IOACPI


//TX_DISABLE and RX_DISABLE should be 0 ,if a GPIO is configured as NFx.
PIN:GPP_A0  DW1,DW0:00000018,84000502 FUNC:NF1  PULL:NONE   RESET:PLTRST TX_DISABLE:1 RX_DISABLE:0 RXINV:NONE   TRIG:OFF         ROUTE:
PIN:GPP_A1  DW1,DW0:00003019,84000402 FUNC:NF1  PULL:UP_20K RESET:PLTRST TX_DISABLE:0 RX_DISABLE:0 RXINV:NONE   TRIG:OFF         ROUTE:
PIN:GPP_A2  DW1,DW0:0000301a,84000402 FUNC:NF1  PULL:UP_20K RESET:PLTRST TX_DISABLE:0 RX_DISABLE:0 RXINV:NONE   TRIG:OFF         ROUTE:
PIN:GPP_A3  DW1,DW0:0000301b,84000402 FUNC:NF1  PULL:UP_20K RESET:PLTRST TX_DISABLE:0 RX_DISABLE:0 RXINV:NONE   TRIG:OFF         ROUTE:
PIN:GPP_A4  DW1,DW0:0000301c,84000402 FUNC:NF1  PULL:UP_20K RESET:PLTRST TX_DISABLE:0 RX_DISABLE:0 RXINV:NONE   TRIG:OFF         ROUTE:
PIN:GPP_A5  DW1,DW0:0000001d,84000600 FUNC:NF1  PULL:NONE   RESET:PLTRST TX_DISABLE:0 RX_DISABLE:1 RXINV:NONE   TRIG:OFF         ROUTE:



Thank you very much，if you can help me.


Wang Xiang
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20180418/9e152cbd/attachment.html>