[coreboot] Runtime config
jwerner at chromium.org
Fri Apr 13 21:55:02 CEST 2018
> And you seem to assume that CBFS is memory mapped which might not always
> be the case.
This is a very important part to keep in mind when we are talking UART.
There has been an attempt inside the Chrome OS team before to make the UART
runtime-configurable, and it fell flat on its face because of this. On a
non-x86 system, the purpose of the whole bootblock is essentially just to
get the SPI flash up and running far enough that you can read it. So if you
need to read SPI flash before you can initialize the UART, the whole
bootblock and all the places where stuff might go wrong that you'd need a
UART to debug is essentially already over. If you want to allow any runtime
configuration for the UART, you'll probably have to contend that it only
works in verstage/romstage or later.
Also, please keep in mind that some users care more than others about the
boot speed impact from reading runtime configuration, so always leave the
option open to keep it all hardcoded and fast.
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