[coreboot] Fwd: POST cards, I/O ports and M.2 to MiniPCIe

[Kyösti Mälkki]

Hi

On Tue, Apr 3, 2018 at 5:36 PM, Trammell Hudson <hudson at trmm.net> wrote:
> How soon after reset are port 0x80 messages available on a MiniPCIe
> attached POST card?  And would the POST card be expected to work with
> a M.2 to MiniPCIe adapter?  How is the ISA bus' I/O address space mapped
> to PCIe devices?
>

First read this:
https://mail.coreboot.org/pipermail/coreboot/2018-February/086178.html

So those POST displays are not PCIe at all but LPC. Some bits to route
IO port 0x80 to LPC is typically set early in romstage but it could be
done in bootblock if needed.

The low end of IO range 0x0..0x1000 is usually reserved for integrated
devices within SoC or PCH with fixed assignments.

> I'm dealing an early bring-up problem on a modern architecture without
> serial ports and wondering if that would a good way to debug it.

Probably M.2 is not very useful for you... try to look for LPC
signals, some boards have TPM add-on connector with the required
signals for POST display.

Certain mini-PCI-e serial port cards and usbdebug are better
alternatives and can work for early romstage. But I guess you no
longer have EHCI controller and the tree does not have xHCI debugging
in production quality at least.

HTH
Kyösti