[coreboot] SATA init on FSP 2.0 for Skylake

[Naresh G. Solanki]

Hi,

Looking at

coreboot-4.7-51-g2ca4ca3f21-dirty Thu Jan 18 22:05:03 UTC 2018
romstage starting...
pm1_sts: ffff pm1_en: ffff pm1_cnt: ffffffff
gpe0_sts[0]: ffffffff gpe0_en[0]: ffffffff
gpe0_sts[1]: ffffffff gpe0_en[1]: ffffffff
gpe0_sts[2]: ffffffff gpe0_en[2]: ffffffff
gpe0_sts[3]: ffffffff gpe0_en[3]: ffffffff

It seems to me that PM base is not setup properly.(this should be fixed first)


Also before you use SATA, make sure FspSUpd for sata is set to be
enabled. Also respective sata port is enabled.

Above that, also check in fit tool whether right setting is done for
flex io for sata port.


On Sun, Apr 1, 2018, 6:43 PM Zheng Bao <fishbaoz at hotmail.com> wrote:

> I met the same problem. I use the FSP1.1 and the 0:17h:0 disappears after
> raminit.
> It seems that the FSP disable the SATA.
>
> The SATA device can be disabled if SCFD is set. But it can not re-enable.
>
> SATA Controller Function Disable (SCFD): BIOS program this bit to 1 to
> disable
> the SATA Controller function. When 0, SATA Controller function is enabled.
> When
> disable, SATA Host Controller will not claimed the register access
> targeting its
> Configuration Space. In IOSF primary Fabric Decode scheme, it's expected
> BIOS also
> program the corresponding bit used by the Fabric Decoder accordingly hence
> both
> SATA SIP and Fabric Decoder are in sync, and BIOS need to program this bit
> before
> programming the one in Fabric Decoder. Once this bit is set, BIOS isnot
> able to revert
> it back to Function Enable until next round of platform reset.
>
> Zheng
>
> ------------------------------
> *From:* coreboot <coreboot-bounces at coreboot.org> on behalf of roman
> perepelitsin <perepelitsin.roman at gmail.com>
> *Sent:* Wednesday, March 28, 2018 2:51 PM
> *To:* coreboot at coreboot.org
> *Subject:* [coreboot] SATA init on FSP 2.0 for Skylake
>
> Hi!
> I got a little problem with SATA controller in H110 Skylake PCH (desktop).
> SATA device geographical address - 0:17h:0 on PCI, and it enabled via
> devicetree.cb. This params correctly send in FspSiliconInit. After this
> coreboot run PCI bus scan. And my SATA device return 0xffffffff on PCI read
> config cycles. I search in Intel datasheet for specific SATA disable pin or
> something else, but there is no methods that can make SATA inactive. Maybe
> somebody advice about it?
>
>
>
> --
> regards,
> Perepelitsin Roman
> --
> coreboot mailing list: coreboot at coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20180403/2419df5a/attachment.html>