[coreboot] SMM save area in MSRs on newer intel CPUs

Aaron Durbin adurbin at google.com
Sun Oct 8 05:58:50 CEST 2017

haswell and on has this. You can see it in the haswell code. We
actually opted not to use it but for relocation so we could look at
each cpu's save state from a single cpu to see who caused the smi,

On Sat, Oct 7, 2017 at 8:38 AM, ron minnich <rminnich at gmail.com> wrote:
> can someone point me at the documents that describe how this works?
> thanks
> ron
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