[coreboot] Some qustion about riscv implement

[王翔]

# Some qustion about riscv implement


## 1. SMP


Coreboot for riscv does not support SMP, now. 
why does the secondary hart not halt in **src/arch/riscv/bootblock.S**?
Now, secondary hart halts in **src/arch/riscv/trap_util.S**.
This may affect playload implementation.




## 2. Privilege level for hypervisor


Privilege level2 is Reserved In newest **rescv-privileged-v1.10.pdf**.
According to the latest **rescv-privileged-v1.10.pdf**, the privilege level 2 is
reserved. However, it appears in the source code. 




## 3. Exception 


Both **supervisor_trap_entry** and **trap_entry** in 
**src/arch/riscv/trap_util.S** have similar functionality. The only difference 
is the latter halts the secondary hart. **supervisor_trap_entry** is unused 
currently, what's the purpose of that?


The two restore context handlers **supervisor_call_return** 
**machine_call_return** in **src/arch/riscv/trap_util.S** are the same and 
they're in another section. Why not put these codes right after 
**supervisor_trap_entry**/**trap_entry** so there's no need to insert assembly 
codes in **src/arch/riscv/trap_handler.c**.




## 4. CSR(mtime mtimecmp)


Hart-local storage records the address of mtime/mtimecmp. However, I could not 
find information regarding CSR mapped to memory space in the latest document 
**rescv-privileged-v1.10.pdf**.




## 5. S/M Privilege level use same stack


Function **riscvpayload** in **src/arch/riscv/payload.S** does not create a new
stack for S privilege level. This may destroy the stack of M privilege level.







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王翔

安全研究员

广州市腾御安信息科技有限公司





广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024
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