[coreboot] PCIe Role-based error reporting

[Youness Alaoui]

Hi,

I'm looking at the src/device/pciexp_device.c file trying to understand
what it does and I've noticed this in pciexp_enable_aspm :
/* Enable ASPM role based error reporting. */
devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
devcap |= PCI_EXP_DEVCAP_RBER;
pci_write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap);

This looks like it tries to write a bit to 1 to enable Role-based
error-reporting in the DEVCAP (offset 0x04) in the PCIe capability, but
according to the spec (looking at page 612 of the spec version 3.0 that I
found here  :
http://composter.com.ua/documents/PCI_Express_Base_Specification_Revision_3.0.pdf),
that structure is read-only (it's the device capabilities register, not the
device control register).
Is that an error ?
I tracked that code (moved, then moved again) all the way to this change
from 2011 : https://review.coreboot.org/#/c/735/ but for some reason git
blame can't find the file in commits before that.

That code is probably harmless since it's a Read-only field anyways, but
I'm wondering if the code that should be there shouldn't instead be
enabling the bits 0:3 in the device control register to enable the error
reporting. Also, I don't see how this actually relates to ASPM (it only
gets called if ASPM is enabled).

Does anyone know if I'm on the right track in my interpretation or if I
misunderstood the spec or what that code is meant to do ?

Thanks,
Youness.
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