[coreboot] [PATCH] nb/intel/nehalem/raminit.c: Add timeouts when waiting for heci.

[Denis 'GNUtoo' Carikli]

Since until now, the code running on the management engine is:
- Signed by its manufacturer
- Proprietary software, without corresponding source code
It can desirable to run the least ammount possible of such
code, which is what me_cleaner[1] enables.

It does it by removing partitions of the management engine
firmwares, however when doing so, the HECI interface might
not be present anymore.

So it is desirable not to have the RAM initialisation code
wait forever for the HECI interface to appear.

[1] https://github.com/corna/me_cleaner/

Change-Id: Iebafa353ecd8875395d6c3a986da6082772e2e18
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
 src/northbridge/intel/nehalem/raminit.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 122b8ac7cf..27065d139e 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1753,23 +1753,27 @@ static const struct ram_training *get_cached_training(void)
 }
 #endif
 
-/* FIXME: add timeout.  */
 static void wait_heci_ready(void)
 {
-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8));	// = 0x8000000c
+	int i = 1000*1000;
+
+	while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */
+		udelay(1);
 	write32((DEFAULT_HECIBAR + 0x4),
 		(read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
 }
 
-/* FIXME: add timeout.  */
 static void wait_heci_cb_avail(int len)
 {
+	int i = 1000*1000;
+
 	union {
 		struct mei_csr csr;
 		u32 raw;
 	} csr;
 
-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8));
+	while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8))
+		udelay(1);
 
 	do
 		csr.raw = read32(DEFAULT_HECIBAR + 0x4);
-- 
2.12.1