[coreboot] ASUS F2A85-M ROM Stage Behavior

Berj K Chilingirian berjc at mit.edu
Mon Mar 20 23:16:44 CET 2017

Hi Kyösti,

Building coreboot with HUDSON_LEGACY_FREE disabled fixed it! Thank you for your help and fast reply!

On Mar 20, 2017, at 7:27 AM, Kyösti Mälkki <kyosti.malkki at gmail.com<mailto:kyosti.malkki at gmail.com>> wrote:

On Mon, Mar 20, 2017 at 11:51 AM, Berj K Chilingirian <berjc at mit.edu<mailto:berjc at mit.edu>> wrote:
Dear Coreboot Community,I also have a serial port adapter (to USB) so that I can see the output of the coreboot process. Using this setup I am able to start up the machine with coreboot and get to the coreinfo screen (which I can then interact with).

I am confused, however, by the output I am seeing from the boot process (attached). Specifically, it appears that the AmdInitReset procedure never exits, as shown below.

coreboot-4.5-1349-g41dded3-dirty Mon Mar 20 03:04:09 UTC 2017 romstage starting... POST: 0x34 BSP Family_Model: 00610f21 cpu_init_detectedx = 00000000 POST: 0x37 AmdInitReset: Start *** !!AGESA cb_AgesaV0.0.0.1 *** FCH Reset Data Block Allocation: [0x0], Ptr = 0x004001e0 Fch OEM config in INIT RESET Done PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 subsystem <- 1022/1410 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0003 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0003


I think this is just a case that the routing of serial port IO address range to LPC bus and further down to the UART is blocked as part of AmdInitReset. And we recover it as part of device resource assignment late in ramstage.

Try build with HUDSON_LEGACY_FREE=n, should be visible "System is legacy free" choice in menuconfig. The help text there does not really match what it does and default setting seems incorrect for all the cases where board has super-io and serial port.


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