[coreboot] soc/amd/stoneyridge

Paul Menzel paulepanter at users.sourceforge.net
Sat Jun 10 12:33:32 CEST 2017

Dear Marc,

Thank you for bringing this up on the coreboot mailing list.

Am Dienstag, den 16.05.2017, 22:37 +0000 schrieb Marc Jones:

> We want to bring to your attention   the following patches, which are the
> start of an experiment to move AMD coreboot SOCs to the same structure as
> other vendor SOCs.
> https://review.coreboot.org/#/q/topic:soc_stoneyridge
> The goals of the experiments are:
> - to correct interfaces for each coreboot stage
> - to leverage common coreboot drivers (which require the common soc
> structure)
> - to correct nagging issues in current implementations (cruft, bit-rot, etc)
> - to provide an example for AMD silicon and mainboards moving forward
> We recognize that these changes may not be compatible with the current
> binaryPI API (AGESA2008 a.k.a. v5),

Could you please elaborate where the API is broken?

> so the separation allows current AGESA and binaryPI solutions to be
> maintained and developed independently. Once stable, we expect that
> changes may be back-ported or older silicon brought up to the new soc
> structure.

Seeing the lack of manpower for AMD systems, I am concerned about
two(?) solutions that need to be maintained. If the current experiment
succeeds, there should be a roadmap how the current boards will be


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