[coreboot] BUG : riscv register address is incorrect

王翔 merle at tya.email
Tue Jun 6 11:04:09 CEST 2017


I tried using spike to debug the coreboot code. But encountered a problem: **mcounteren/smcounteren** address is not correct.


The bug code is in `src/arch/riscv/virtual_memory.c`
```
313     // Enable all user/supervisor-mode counters using
314     // v1.9.1 register addresses.
315     // They moved from the earlier spec.
316     // Until we trust our toolchain use the hardcoded constants.
317     // These were in flux and people who get the older toolchain
318     // will have difficult-to-debug failures.
319     write_csr(/*mcounteren*/0x320, 7);       //this address shoud fix to 0x306
320     write_csr(/*scounteren*/0x321, 7);        //this address shoud fix to 0x106

```
I have already submitted a patch.
https://review.coreboot.org/#/c/20043/





------------------



王翔

安全研究员

广州市腾御安信息科技有限公司





广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024
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