[coreboot] Problem with implementing workaround from errata

[Łukasz Dobrowolski]

On 07/23/2017 01:29 PM, Kyösti Mälkki wrote:
> Hi
> 
> Please mention the errata document number, looks like the attachment
> was dropped.
It's 47792 (AMD A45/A50M/A55E Errata).

> Also you can just post your work-in-progress source to gerrit,
> including the workaround you have implemented.
I don't know where to start with the workaround.
I'll clean up the code and submit it later today.

> Kyösti
> 
> On Sun, Jul 23, 2017 at 10:10 AM, Łukasz Dobrowolski
> <lukasz at dobrowolski.io> wrote:
>> Hi!
>> I've resumed my work non ThinkPad X120e.
>>
>> I have a problem with random hangs during boot.
>> The hang occurs in vendorcode/amd/cimx/sb800/SBPort.c:296.
>>
>> After a long fight I was able to diagnose the issue. It's described in
>> errata (attached) on page 13. There is a suggested workaround, however
>> the description is not verbose enough for me.
>>
>> Could somebody give me some hints?
>>
>> The functions are entered in this order:
>> (?)
>> cache_as_ram_setup: //cpu/amd/agesa/cache_as_ram.inc
>> void * asmlinkage romstage_main(unsigned long bist)
>> //cpu/amd/agesa/romstage.c
>> void platform_once(struct sysinfo *cb) //cpu/amd/agesa/family14/romstage.c
>> void sb_Poweron_Init(void) //southbridge/amd/cimx/sb800/early.c
>> VOID sbPowerOnInit(IN AMDSBCFG* pConfig)
>> //vendorcode/amd/cimx/sb800/SBPort.c (hang!)
>>
>> Where should I put the workaround if I can't pollute the shared code?
>>
>> The code for the port is based on asrock/e350m1. I can upload it to
>> gerrit if needed but not much was changed.
>>
>> --
>> Łukasz Dobrowolski
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> https://mail.coreboot.org/mailman/listinfo/coreboot


-- 
Łukasz Dobrowolski