[coreboot] T530: Cleaning Intel ME currently does not work <--> CPU fan won't start

David Hobach tripleh at hackingthe.net
Sat Jul 22 09:57:39 CEST 2017


>> On 20.07.2017 23:48, Pavel Alyev wrote:
>>>
>>> Not at all. ME can control clock output frequency at GPIO 64/65/66/67.
>>> From coreboot you can only set these pins to NATIVE mode. So, if you
>>> EC/SIO take clock input from PCH, without ME they may work incorrectly.
>>
>> you are right. I forgot that the ThinkPad EC is more a Super-I/O and may
>> need the PCH to work (and not the other way around). And it's indeed
>> connected to SUSCLK (GPIO62). Although I don't know what it does with
>> that clock, it's possible that the ME messes with it.
>>
>>>
>>> But looks like at t530 this outputs sets in GPIO mode. David, can you
>>> dump gpios from system with running ME (can be done by 'inteltool -g').
>
> Did that for both flashes, logs are attached (also includes journalctl
> and cbmem logs).
>
> The only difference I noticed from the cbmem logs though was that
> apparently without ME coreboot only sees 8GB/16GB of memory?
> Still, the fan didn't spin without ME after a hard reset. It once again
> did spin before I did the hard reset...
>
> I also tried to get the cbmem logs before the truncation note, but
> couldn't find out how to enable PRERAM_CBMEM_CONSOLE_SIZE (I guessed
> that's the relevant option).
>
> inteltool -g shows a difference for only
> gpiobase+0x0000: 0x3962a5ff (GPIO_USE_SEL) <-- with ME
> gpiobase+0x0000: 0xb962a5ff (GPIO_USE_SEL) <-- without ME

P.S.: Just tested the current ME-cleaner version with the OEM BIOS 
version: The CPU fan did spin - even after hard resets.

So
a) The issue is only related to coreboot.
b) It is possible to do better here.

(I also attached the inteltool output of that test - not sure whether 
it's relevant.)

> @Flashing: I did use external flashing with the powered T530 in the
> past, but today it stopped working reliably for the 8M chip (the 4M
> still worked), so I switched to internal from Fedora now. flashrom
> reported verification success for that. Further details wrt external
> flashing method:
> https://mail.coreboot.org/pipermail/flashrom/2017-July/015043.html
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CPU: ID 0x306a9, Processor Type 0x0, Family 0x6, Model 0x3a, Stepping 0x9
Northbridge: 8086:0154 (3rd generation (Ivy Bridge family) Core Processor (Mobile))
Southbridge: 8086:1e55 (QM77)
IGD: 8086:0166 (unknown)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb962a5ff (GPIO_USE_SEL)
gpiobase+0x0004: 0x8ebf6aff (GP_IO_SEL)
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe6b77efb (GP_LVL)
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00000000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
gpiobase+0x002c: 0x00002042 (GPI_INV)
gpiobase+0x0030: 0x02ff08fe (GPIO_USE_SEL2)
gpiobase+0x0034: 0x1f47f7fd (GP_IO_SEL2)
gpiobase+0x0038: 0xbfbaff43 (GP_LVL2)
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000000ff (GPIO_USE_SEL3)
gpiobase+0x0044: 0x00000fff (GP_IO_SEL3)
gpiobase+0x0048: 0x00000f4f (GPIO_LVL3)
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1)
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)


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