[coreboot] logical error for smm hander in coreboot.

[Zoran Stojsavljevic]

Hello Tang,

Not sure what is actually your question here? If you have 4 cores in your
mainboard, the BIOS (any BIOS, looking into SEC + PEI phases), will work on
the following way (more or less, it is view from 37000 feet, where
commercial jetliners operate):
[1] BIOS on main CPU will start after EC configures PMIC and PCH does the
original HECI setup;
[2] All four cores will be let go out of hard reset state, but they will
compete who is the system one, and who are so-called application
processors; The first which will configure the bare minimum wins, and it'll
be Core 0 (called BSP - BootStrap Processor), all others will be Cores X, X
= [1..3], application ones;
[3] Core 0 (BSP) will continue running BIOS code, all others (application)
cores will be put in waiting state, waiting for SIPI (Startup
Inter-Processor Interrupt), send via BSP's LAPIC (MSIs - Message Serviced
Interrupts are not allowed in BIOS);
[4] While BSP runs, it runs also entering several times SMM mode using SMI,
in order to set ACPI (Advanced Configuration and Power Interface) tables,
or similar...

Coreboot people can compare if the similar, described above) is happening
with Coreboot code. Should, in my opinion (so NO multiprocessing done in
Coreboot, my best guess). For x86 and x86_64 architectures.

Zoran

On Tue, Jan 3, 2017 at 4:20 AM, Tang Tank <js_nj_tanktang at outlook.com>
wrote:

>
> Hi all,
>
>
>    For smm handler (func smm_handler_start) in
> coreboot/src/cpu/x86/smm/smm_module_handler.c,
> there may be a logical error.
>
>    If I have 4 cores in my mainboard in the following special conditions:
>    1. core0 run into smm_handler_start and smi_handler_status will be
> SMI_LOCKED.
>    2. core1/2 run into smm_handler_start and pause since
> smi_handler_status is locked.
>    3. core0 release smi_handler_status and then core4 run into
> smm_handler_start, it will do
>        southbridge_smi_handler again.
>
>    So is there have a reliable way of doing smm multi processors services
> in coreboot?
>
>
> Thanks
> Tank
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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