[coreboot] SPI Flash Writeprotect

[Stefan Reinauer]

* John Lewis <jlewis at johnlewis.ie> [170227 10:38]:
> Hi Naveed,
> 
> It's probably the MRC cache or something like that, which IIRC you can disable.

This is correct. Unfortunately, if you disable the MRC cache you will
lose functionality like the ability to resume from S3 suspend, and your
boot time will go up between 300ms and 30 some seconds, depending on the
chipset you are looking at.

Stefan

> Whether there is also something else writing to the chip from coreboot I'm not
> 100% but others will chime in on that, I'm sure.
> 
> Kind Regards,
> 
> John.
> 
> 
> On 27/02/17 08:15, Naveed Ghori wrote:
> 
> 
>     Hi all,
> 
>     Does Coreboot write to the flash chip it resides on? Can this be disabled?
> 
>     Verify of the SPI bios chip fails once the unit has booted up at least
>     once.
> 
>      
> 
>     Best Regards,
> 
>     Naveed
> 
>     Naveed Ghori | Lead Firmware & Driver Engineer
>     DTI Group Ltd | Transit Security & Surveillance
>     31 Affleck Road, Perth Airport, Western Australia 6105, Australia
>     P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.ghori at dti.com.au
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