[coreboot] Add coreboot storage driver

[Zoran Stojsavljevic]

Listen Timothy....

INTEL is FW (we can argue here, I do agree) and SW (NOT at all any
argument, it is an aksioma) very crappy company. I know that INTEL CCG
directors ordered people to watch me over, and, personally, I do NOT care.
Really I don't. I worked for 5 years for INTEL support in Bavaria.

But let me tell you one thing. Whatever/However I do NOT (somehow) trust to
INTEL FW and especially (in concrete) TO SW (mostly piece of junk, they
produce), I will give my life in/to IA (INTEL Architecture) HW top-notch
designers hands. Blindly. Now. Ever!

INTEL has IA HW group, which is The Best of The Best. I (opposing that I
should NOT know them) know couple of guys there. And they... Are... !

They can make this what I am proposing (not only me) happen. It is just
about The (Crapy) Politics. OK?

Zoran [OUT]

On Tue, Feb 14, 2017 at 8:45 PM, Timothy Pearson <
tpearson at raptorengineering.com> wrote:

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> On 02/14/2017 01:36 PM, Zoran Stojsavljevic wrote:
> >> Where do we go from here?
> >
> > As I said (and I'll repeat, many times, if required - I do NOT care what
> > all INTEL [all their 13000+ managers] think):
> >
> > /I have another idea for INTEL SoCs/CPUs, as HW architecture
> > improvement. Why your top-notch HW guys do NOT implement MRC as part of
> > MCU. Some HW thread inside CPU/SoC should execute MCU, shouldn't it?
> > MRCs should be few K in size, and they can perfectly fit in there, thus
> > MRC should be (my take on this) part of internal CPU architecture./
>
> I highly doubt this would ever happen, unless it's yet another signed
> blob with highly privileged access.  The main problem is that memory
> initialisation is very complex, and there is a definite need to be able
> to issue updates when / if a CPU / MB / DIMM combination fails to
> function correctly.
>
> Personally, having worked on RAM initialisation for many different
> systems (embedded to server), I find it ludicrous that this can be
> considered top secret IP worthy of a closed blob.  It takes time to get
> right, but the end result is inextricably tied to the hardware in
> question and is really not much more than a hardware-specific
> implementation of the bog-standard and widely known DDR init algorithms.
>
> Intel, why the blob?  What's hiding in there?  Asian companies I know
> tend to keep things closed to avoid patent lawsuits over stolen IP, but
> I highly doubt you have this problem?
>
> Just my *personal* $0.02 here. :-)
>
> - --
> Timothy Pearson
> Raptor Engineering
> +1 (415) 727-8645 (direct line)
> +1 (512) 690-0200 (switchboard)
> https://www.raptorengineering.com
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