[coreboot] Early debugging

[Gergely Kiss]

Hi Kyösti,

thanks for the thorough reply!

The base address for the SIO should be fine as superiotool's output tells
me the chip is available at 0x2e, it can even return the model number and
the revision but unfortunately no other information:

Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0x8623, rev=0x1

I guess I would need to implement support for this chip in superio's code
to get more information. Maybe I'll try implementing it until my POST card
arrives but it won't be easy without the datasheet, I'm afraid.

The code in romstage.c sets the oscillator clock to 48MHz and enables
decoding for the needed base addresses, I have verified that part against
the register reference guide and it should be correct.

The problem can be that SIO devices are at some unusual addresses for the
IT8623E chip. If my assumption is right, serial ports use LDNs 0x06 and
0x07, at least they appear on the PNP bus with IDs 00:07 and 00:08 (not
sure if the these two are related):

*** /sys/bus/pnp/drivers/serial/00:07/:
total 0
lrwxrwxrwx 1 root root    0 Dec  1 19:52 driver ->
../../../bus/pnp/drivers/serial
lrwxrwxrwx 1 root root    0 Dec  1 19:52 firmware_node ->
../../LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:0d/PNP0501:00
-r--r--r-- 1 root root 4096 Dec  1 19:52 id
-r--r--r-- 1 root root 4096 Dec  1 19:52 options
drwxr-xr-x 2 root root    0 Dec  1 19:52 power
-rw-r--r-- 1 root root 4096 Dec  1 19:42 resources
lrwxrwxrwx 1 root root    0 Dec  1 19:52 subsystem -> ../../../bus/pnp
drwxr-xr-x 3 root root    0 Dec  1 19:52 tty
-rw-r--r-- 1 root root 4096 Dec  1 19:52 uevent

*** /sys/bus/pnp/drivers/serial/00:08/:
total 0
lrwxrwxrwx 1 root root    0 Dec  1 19:52 driver ->
../../../bus/pnp/drivers/serial
lrwxrwxrwx 1 root root    0 Dec  1 19:52 firmware_node ->
../../LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:0d/PNP0501:01
-r--r--r-- 1 root root 4096 Dec  1 19:52 id
-r--r--r-- 1 root root 4096 Dec  1 19:52 options
drwxr-xr-x 2 root root    0 Dec  1 19:52 power
-rw-r--r-- 1 root root 4096 Dec  1 19:43 resources
lrwxrwxrwx 1 root root    0 Dec  1 19:52 subsystem -> ../../../bus/pnp
drwxr-xr-x 3 root root    0 Dec  1 19:52 tty
-rw-r--r-- 1 root root 4096 Dec  1 19:52 uevent

/sys/bus/pnp/drivers/serial/00:07/resources
state = active
io 0x3f8-0x3ff
irq 4
dma disabled
/sys/bus/pnp/drivers/serial/00:08/resources
state = active
io 0x2f8-0x2ff
irq 3
dma disabled

I have a feeling the boot process doesn't even reach the part where the
serial port would be initialized, maybe due to missing some crucial GPIO
configuration or the lack of proper implementation of AM1 socket support -
both can be possible but first I'd need to have a POST card at hand.

Is there some guide available on how to dump GPIO configuration for AMD
boards? inteltool is a very handy utility for Intel boards, I wonder if
there is some similar tool for AMD based boards? amdtools seems to support
K8 only.

iotools is also very useful for checking register settings but to use it,
I'd need to know how to access the GPIO pins - as far as I can see, it can
be either through the SIO chip (the harder way) or directly by querying
certain (MMIO?) addresses which should be easy if the proper addresses to
query are known. I think I'll have to dig a bit deeper into the
southbridge's databook to find that out.

Regards,
Gergely

On 4 December 2017 at 18:42, Kyösti Mälkki <kyosti.malkki at gmail.com> wrote:

> On Mon, Dec 4, 2017 at 2:44 PM, Gergely Kiss <mail.gery at gmail.com> wrote:
> > Hi,
> >
> > I'm working on porting Coreboot to the ASUS AM1I-A motherboard and I'm a
> bit
> > stuck.
> >
> > I could successfully build Coreboot but after flashing the ROM, my board
> > looks to be bricked...
> >
> > Once powering on the board, the CPU fan spins up but then nothing
> happens, I
> > can't see any output on the serial console (the connection was tested
> prior
> > to flashing by running a getty on the COM port and it was working fine).
> >
>
> Common errors: Forgetting to use correct super-IO config base address
> (0x2e vs 0x4e) and not providing 48MHz reference clock for the uart
> baudrate divisor. AMD hardware often uses configurable GPIO pins for
> this purpose, the code copied from biostar/am1ml may not be right for
> asus/am1l-a.
>
> You can dump those GPIO configurations eg. with iotools or even dd
> from /dev/mem. Related datasheets for the Kabini family should be
> available without NDAs.
>
> > The board is not fried as I can load back the vendor firmware and it
> boots
> > up absolutely fine.
> >
> > I'd like to find out why Coreboot would not start but don't know what
> tool
> > would be the most suitable for debugging.
> >
> > The chipset and the CPU is already supported by Coreboot but the SuperIO
> > chip is not. It looks to me the serial interfaces of ITE chips work the
> same
> > for all models so I believe using the common code for ITE SIO chips
> should
> > work but I'm unsure (no datasheet available).
>
> AM1 socket support is a hack anyways, grep for
> FORCE_AM1_SOCKET_SUPPORT. Your mileage may vary.
>
> It's not uncommon that PNP LDNs for the UARTs change within one vendor.
> Did you run util/superiotool and dump SIO settings from vendor boot?
>
> >
> > Shall I use a PCIe serial interface card or rather try EHCI debugging?
> I'm
> > afraid in case the boot process halts at some early stage (like before
> > romstage) then I won't see any useful output using any of those.
> >
>
> EHCI debug should be fine nowadays with AGESA, still not my first
> choice here for you.
> PCIe serial cards are untested, probably do not work early enough to
> be useful for you.
> Traditional serial port debug will also be silent before romstage...
>
> > Using a POST card would be a better approach I think but my board has a
> > single PCIe 4x slot which seems to be unsupported by POST cards I could
> find
> > on the web (except one from a Chinese vendor but it costs about $1k
> which is
> > way too expensive).
>
> Those mini-PCI-e POST cards with 7-seg displays are about 4 USD and
> your mainboard TPM connector seems to carry the required LPC signals.
> Remember to enable and route POSTs to LPC (kconfig POST_DEVICE_LPC).
>
> >
> > Here's my WIP code for reference:
> >
> > https://github.com/kissg1988/coreboot/tree/master/src/
> mainboard/asus/am1i-a
> >
> > Any idea how to proceed?
> >
>
> Get one of those POST cards, try to show vendor/device ID registers
> from superio on the 7-seg display.
>
> > Thanks,
> > Gergely
> >
> >
>
> HTH,
> Kyösti
>
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > https://mail.coreboot.org/mailman/listinfo/coreboot
>
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