[coreboot] Need help implementing romstage CBMEM

Thu Aug 31 23:34:40 CEST 2017

Oops, I've attached the boot log of a previous failed attempt. This
boot log should be the correct one.

On Thu, Aug 31, 2017 at 1:29 PM, Keith Hui <buurin at gmail.com> wrote:
> On Wed, Aug 30, 2017 at 6:49 PM, Kyösti Mälkki <kyosti.malkki at gmail.com> wrote:
>> On Wed, Aug 30, 2017 at 11:39 PM, Keith Hui <buurin at gmail.com> wrote:
>>> Hi guys,
>>>
>>> I'm still hard at work over the venerable (even "almighty" at the
>>> time) 440BX and Slot 1 boards.
>>>
>>> [1] https://review.coreboot.org/c/20977/
>>>
>>> And now I'm stuck and thoroughly confused.
>>>
>>> My current state is:
>>> 1. cbmem_initialize_empty() failed to even start allocating the root
>>> CBMEM entry. No indication why. I tried tracing the code path in the
>>> sources and still could not find out where exactly it failed. With
>>> enough fiddling I did get it to complain the way Aaron expected [1].
>>
>> Please update your work in gerrit, showing all the actual code changes
>> you try to boot with. This includes changes under mainboard/.
>>
>>> 2. Using the common Intel CPU cache_as_ram.inc, I can get through
>>> mainboard romstage and memory init. If I just return a fixed
>>> CONFIG_TOPMEM in setup_stack_and_mtrrs() like what was done in
>>> cpu/intel/nehalem, it got past the point of POST_PREPARE_RAMSTAGE and
>>> then nothing.
>>
>> All that setup_stack_and_mtrrs() is not really required for
>> EARLY_CBMEM_INIT, leave all that as followup work. Use unmodified
>> car/romstage_legacy.c and car/cache_as_ram.inc with that
>> DCACHE_RAM_BASE fixed.
>>
>> Disable CBMEM console and timestamps for the time being, as those eat
>> a lot of your CAR allocation. Those may have smashed your stack in CAR
>> to the extent of breaking raminit.
>>
>>> 3. Porting the postcar frame assembly from
>>> cpu/intel/car/cache_as_ram_ht.inc results in a failure somewhere
>>> before loading ramstage and after
>>
>> Push your modified source to gerrit if you want comments on that.
>>
>>> 4. If I try to run this build under QEMU, it fails with "Trying to
>>> execute code outside RAM or ROM at 0x000a0000" in 440BX RAM init code
>>> after dumping the "before" northbridge config, so I can't correctly
>>> debug it this way either.
>>
>> Just forget about using QEMU for the task at hand.
>>
>> Kyösti
>
> Thanks for the tips Kyösti. Nothing like hearing it from the source. :)
>
> I've updated gerrit again following your tips. This update actually
> boots! Boot log attached.
>
> For cache_as_ram.inc I just dropped CacheBase/CacheSize and have it
> use the Kconfig settings directly. I also increased the CAR size to
> 8k.
>
> Q1: Would this qualify as cbmem in romstage?
>
> Set up stack and MTRRs in cpu/intel/slot_1
> cbmem_top() and associated top of RAM calculations go to nb/intel/i440bx.
>
> Q2: Are these the right places for these codes?
> All Slot 1 boards currently in tree use 440BX and much of them seem
> unmaintained. I only have 3 of them (-LS, P3B-F, -DS) and I don't have
> a second matching P3 CPU to test the DS. So I want to see if I can
> initialize CBMEM in cpu/intel/slot_1, lest work wasted with all those
> other boards getting dropped past 4.8?
-------------- next part --------------
coreboot-4.6-1081-g23acd5db2d-dirty Thu Aug 31 00:53:14 UTC 2017 romstage starting...

DIMM 0: 50
00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2c 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 af 
40: 25 7f 7f 7f 00 00 00 00 41 4d 50 4a 42 36 33 53 
50: 2d 36 38 4b 58 33 2d 45 42 49 00 00 00 01 00 00 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 1: 51
00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2c 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 af 
40: 7f 7f 7f 25 00 00 00 00 41 4d 50 4a 42 36 33 53 
50: 2d 36 38 4b 58 33 2d 45 42 41 00 00 00 01 00 00 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 2: 52
00: 80 08 04 0c 0a 02 40 00 01 70 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e 75 54 00 00 0f 0e 0f 2d 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 69 
40: 00 43 41 54 32 32 00 00 00 00 00 00 00 00 00 00 
50: 00 08 00 00 00 00 00 00 00 00 00 00 00 06 01 20 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 3: 53
00: bad device

Northbridge prior to SDRAM init:
PCI: 00:00.00
00: 86 80 90 71 06 00 10 22 02 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 04 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
60: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00
70: 00 1f 02 38 00 00 00 00 00 00 00 38 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 02 00 68 53 18 0c 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
Found DIMM in slot 0
DIMM is not registered
Found DIMM in slot 1
DIMM is not registered
Found DIMM in slot 2
DIMM is not registered
PGPOL[BPR] has been set to 0x3f
RPS has been set to 0x0aaa
NBXECC[31:24] has been set to 0x3f
DRAMC has been set to 0x08
RAM Enable 1: Apply NOP
RAM Enable 2: Precharge all
RAM Enable 3: CBR
RAM Enable 4: Mode register set
RAM Enable 5: Normal operation
RAM Enable 6: Enable refresh
    Enabling refresh (DRAMC = 0x09) for DIMM 00
    Enabling refresh (DRAMC = 0x09) for DIMM 01
    Enabling refresh (DRAMC = 0x09) for DIMM 02
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 90 71 06 00 10 22 02 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 0c 80 00 3f 00 00 00 09 03 30 33 33 33 33 33 33
60: 10 20 30 40 50 60 60 60 00 f0 2b 00 a0 ba 00 00
70: 00 1f 02 38 aa 0a 10 00 00 3f 10 38 10 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 02 00 68 53 18 0c e6 ff 5f 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
cbmem DRB7 = 30000000
cbmem tom = 30000000
CBMEM:
IMD: root @ 2ffff000 254 entries.
IMD: root @ 2fffec00 62 entries.
cbmem DRB7 = 30000000
cbmem tom = 30000000
cbmem DRB7 = 30000000
cbmem tom = 30000000
CBFS: 'Master Header Locator' located CBFS at [100:3ffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 448c
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 4580
CBFS: File @ offset 4580 size 15800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 4580
CBFS: Checking offset 19e00
CBFS: File @ offset 19e00 size 95eb
CBFS: Found @ offset 19e00 size 95eb

coreboot-4.6-1081-g23acd5db2d-dirty Thu Aug 31 00:53:14 UTC 2017 ramstage starting...
cbmem DRB7 = 30000000
cbmem tom = 30000000
Moving GDT to 2fffe8c0...ok
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
PCI: 00:06.0: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:04.0: enabled 1
   PNP: 03f0.0: enabled 1
   PNP: 03f0.1: enabled 1
   PNP: 03f0.2: enabled 1
   PNP: 03f0.3: enabled 1
   PNP: 03f0.5: enabled 1
   PNP: 03f0.7: enabled 1
   PNP: 03f0.8: enabled 1
   PNP: 03f0.a: enabled 1
  PCI: 00:04.1: enabled 1
  PCI: 00:04.2: enabled 1
  PCI: 00:04.3: enabled 1
  PCI: 00:06.0: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7190] ops
PCI: 00:00.0 [8086/7190] enabled
PCI: 00:01.0 [8086/7191] enabled
PCI: 00:04.0 [8086/7110] bus ops
PCI: 00:04.0 [8086/7110] enabled
PCI: 00:04.1 [8086/7111] ops
PCI: 00:04.1 [8086/7111] enabled
PCI: 00:04.2 [8086/7112] ops
PCI: 00:04.2 [8086/7112] enabled
PCI: 00:04.3 [8086/7113] bus ops
pwrmgt_enable: gpo default missing in devicetree.cb!
PCI: 00:04.3 [8086/7113] enabled
PCI: 00:06.0 [9005/001f] enabled
PCI: 00:07.0 [8086/1229] enabled
PCI: 00:09.0 [102b/0519] enabled
PCI: 00:0a.0 [1039/0111] enabled
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
scan_bus: scanning of bus PCI: 00:01.0 took 0 usecs
PCI: 00:04.0 scanning...
scan_lpc_bus for PCI: 00:04.0
PNP: 03f0.0 enabled
PNP: 03f0.1 enabled
PNP: 03f0.2 enabled
PNP: 03f0.3 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PNP: 03f0.a enabled
PNP: 03f0.6 enabled
scan_lpc_bus for PCI: 00:04.0 done
scan_bus: scanning of bus PCI: 00:04.0 took 0 usecs
PCI: 00:04.3 scanning...
scan_generic_bus for PCI: 00:04.3
scan_generic_bus for PCI: 00:04.3 done
scan_bus: scanning of bus PCI: 00:04.3 took 0 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 0 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 0 usecs
done
found VGA at PCI: 00:09.0
Setting up VGA for PCI: 00:09.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 0 link: 0
PNP: 03f0.8 missing read_resources
PCI: 00:04.0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:04.0 child on link 0 PNP: 03f0.0
   PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
    PNP: 03f0.0
    PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 03f0.1
    PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 03f0.2
    PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.3
    PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.5
    PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
    PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
    PNP: 03f0.7
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.8
    PNP: 03f0.a
    PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.6
    PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
   PCI: 00:04.1
   PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:04.2
   PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:04.3
   PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
   PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
   PCI: 00:06.0
   PCI: 00:06.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 14
   PCI: 00:06.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:07.0
   PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 1200 index 10
   PCI: 00:07.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 14
   PCI: 00:07.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
   PCI: 00:07.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 2200 index 30
   PCI: 00:09.0
   PCI: 00:09.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
   PCI: 00:09.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 1200 index 14
   PCI: 00:09.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
   PCI: 00:0a.0
   PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:06.0 10 *  [0x0 - 0xff] io
PCI: 00:0a.0 10 *  [0x400 - 0x4ff] io
PCI: 00:04.2 20 *  [0x800 - 0x81f] io
PCI: 00:07.0 14 *  [0x820 - 0x83f] io
PCI: 00:04.1 20 *  [0x840 - 0x84f] io
DOMAIN: 0000 io: base: 850 size: 850 align: 8 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:00.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:09.0 14 *  [0x10000000 - 0x107fffff] prefmem
PCI: 00:07.0 18 *  [0x10800000 - 0x108fffff] mem
PCI: 00:07.0 30 *  [0x10900000 - 0x109fffff] mem
PCI: 00:06.0 30 *  [0x10a00000 - 0x10a1ffff] mem
PCI: 00:09.0 30 *  [0x10a20000 - 0x10a2ffff] mem
PCI: 00:09.0 10 *  [0x10a30000 - 0x10a33fff] mem
PCI: 00:06.0 14 *  [0x10a34000 - 0x10a34fff] mem
PCI: 00:07.0 10 *  [0x10a35000 - 0x10a35fff] prefmem
DOMAIN: 0000 mem: base: 10a36000 size: 10a36000 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:04.0 01 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:04.0 02 base ff800000 limit ffffffff mem (fixed)
constrain_resources: PCI: 00:04.3 01 base 0000e400 limit 0000e43f io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000e3ff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit ff7fffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:850 align:8 gran:0 limit:e3ff
PCI: 00:06.0 10 *  [0x1000 - 0x10ff] io
PCI: 00:0a.0 10 *  [0x1400 - 0x14ff] io
PCI: 00:04.2 20 *  [0x1800 - 0x181f] io
PCI: 00:07.0 14 *  [0x1820 - 0x183f] io
PCI: 00:04.1 20 *  [0x1840 - 0x184f] io
DOMAIN: 0000 io: next_base: 1850 size: 850 align: 8 gran: 0 done
PCI: 00:01.0 io: base:e3ff size:0 align:12 gran:12 limit:e3ff
PCI: 00:01.0 io: next_base: e3ff size: 0 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e0000000 size:10a36000 align:28 gran:0 limit:ff7fffff
PCI: 00:00.0 10 *  [0xe0000000 - 0xefffffff] prefmem
PCI: 00:09.0 14 *  [0xf0000000 - 0xf07fffff] prefmem
PCI: 00:07.0 18 *  [0xf0800000 - 0xf08fffff] mem
PCI: 00:07.0 30 *  [0xf0900000 - 0xf09fffff] mem
PCI: 00:06.0 30 *  [0xf0a00000 - 0xf0a1ffff] mem
PCI: 00:09.0 30 *  [0xf0a20000 - 0xf0a2ffff] mem
PCI: 00:09.0 10 *  [0xf0a30000 - 0xf0a33fff] mem
PCI: 00:06.0 14 *  [0xf0a34000 - 0xf0a34fff] mem
PCI: 00:07.0 10 *  [0xf0a35000 - 0xf0a35fff] prefmem
DOMAIN: 0000 mem: next_base: f0a36000 size: 10a36000 align: 28 gran: 0 done
PCI: 00:01.0 prefmem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff
PCI: 00:01.0 prefmem: next_base: ff7fffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 mem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff
PCI: 00:01.0 mem: next_base: ff7fffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 768 MB
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 1c <- [0x000000e3ff - 0x000000e3fe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:04.0 assign_resources, bus 0 link: 0
PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned
PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned
ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned
ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned
ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned
PCI: 00:04.0 assign_resources, bus 0 link: 0
PCI: 00:04.1 20 <- [0x0000001840 - 0x000000184f] size 0x00000010 gran 0x04 io
PCI: 00:04.2 20 <- [0x0000001800 - 0x000000181f] size 0x00000020 gran 0x05 io
PCI: 00:06.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:06.0 14 <- [0x00f0a34000 - 0x00f0a34fff] size 0x00001000 gran 0x0c mem64
PCI: 00:06.0 30 <- [0x00f0a00000 - 0x00f0a1ffff] size 0x00020000 gran 0x11 romem
PCI: 00:07.0 10 <- [0x00f0a35000 - 0x00f0a35fff] size 0x00001000 gran 0x0c prefmem
PCI: 00:07.0 14 <- [0x0000001820 - 0x000000183f] size 0x00000020 gran 0x05 io
PCI: 00:07.0 18 <- [0x00f0800000 - 0x00f08fffff] size 0x00100000 gran 0x14 mem
PCI: 00:07.0 30 <- [0x00f0900000 - 0x00f09fffff] size 0x00100000 gran 0x14 romem
PCI: 00:09.0 10 <- [0x00f0a30000 - 0x00f0a33fff] size 0x00004000 gran 0x0e mem
PCI: 00:09.0 14 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem
PCI: 00:09.0 30 <- [0x00f0a20000 - 0x00f0a2ffff] size 0x00010000 gran 0x10 romem
PCI: 00:0a.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 1000 size 850 align 8 gran 0 limit e3ff flags 40040100 index 10000000
  DOMAIN: 0000 resource base e0000000 size 10a36000 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
  DOMAIN: 0000 resource base c0000 size 2ff40000 align 0 gran 0 limit 0 flags e0004200 index b
   PCI: 00:00.0
   PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 10
   PCI: 00:01.0
   PCI: 00:01.0 resource base e3ff size 0 align 12 gran 12 limit e3ff flags 60080102 index 1c
   PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60081202 index 24
   PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60080202 index 20
   PCI: 00:04.0 child on link 0 PNP: 03f0.0
   PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
    PNP: 03f0.0
    PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
    PNP: 03f0.1
    PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 03f0.2
    PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.3
    PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.5
    PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
    PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
    PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
    PNP: 03f0.7
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.8
    PNP: 03f0.a
    PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.6
    PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
   PCI: 00:04.1
   PCI: 00:04.1 resource base 1840 size 10 align 4 gran 4 limit 184f flags 60000100 index 20
   PCI: 00:04.2
   PCI: 00:04.2 resource base 1800 size 20 align 5 gran 5 limit 181f flags 60000100 index 20
   PCI: 00:04.3
   PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
   PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
   PCI: 00:06.0
   PCI: 00:06.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
   PCI: 00:06.0 resource base f0a34000 size 1000 align 12 gran 12 limit f0a34fff flags 60000201 index 14
   PCI: 00:06.0 resource base f0a00000 size 20000 align 17 gran 17 limit f0a1ffff flags 60002200 index 30
   PCI: 00:07.0
   PCI: 00:07.0 resource base f0a35000 size 1000 align 12 gran 12 limit f0a35fff flags 60001200 index 10
   PCI: 00:07.0 resource base 1820 size 20 align 5 gran 5 limit 183f flags 60000100 index 14
   PCI: 00:07.0 resource base f0800000 size 100000 align 20 gran 20 limit f08fffff flags 60000200 index 18
   PCI: 00:07.0 resource base f0900000 size 100000 align 20 gran 20 limit f09fffff flags 60002200 index 30
   PCI: 00:09.0
   PCI: 00:09.0 resource base f0a30000 size 4000 align 14 gran 14 limit f0a33fff flags 60000200 index 10
   PCI: 00:09.0 resource base f0000000 size 800000 align 23 gran 23 limit f07fffff flags 60001200 index 14
   PCI: 00:09.0 resource base f0a20000 size 10000 align 16 gran 16 limit f0a2ffff flags 60002200 index 30
   PCI: 00:0a.0
   PCI: 00:0a.0 resource base 1400 size 100 align 8 gran 8 limit 14ff flags 60000100 index 10
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0083
PCI: 00:01.0 cmd <- 00
PCI: 00:04.0 cmd <- 07
PCI: 00:04.1 cmd <- 01
PCI: 00:04.2 cmd <- 01
PCI: 00:04.3 cmd <- 01
PCI: 00:06.0 subsystem <- 9005/001f
PCI: 00:06.0 cmd <- 03
PCI: 00:07.0 cmd <- 03
PCI: 00:09.0 cmd <- 83
PCI: 00:0a.0 cmd <- 01
done.
Initializing devices...
Root Device init ...
CPU_CLUSTER: 0 init ...
Initializing CPU #0
CPU: vendor Intel device 6b1
CPU: family 06, model 0b, stepping 01
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [100:3ffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 448c
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 4580
CBFS: File @ offset 4580 size 15800
CBFS: Found @ offset 4580 size 15800
microcode: sig=0x6b1 pf=0x10 revision=0x0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
microcode: updated to revision 0x1c date=2001-02-15
CPU: Intel(R) Celeron(TM) CPU                1400MHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000030000000 size 0x2ff40000 type 6
0x0000000030000000 - 0x00000000f0000000 size 0xc0000000 type 0
0x00000000f0000000 - 0x00000000f0800000 size 0x00800000 type 1
0x00000000f0800000 - 0x0000000100000000 size 0x0f800000 type 0
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 11/3.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000fe0000000 type 6
MTRR: 1 base 0x0000000020000000 mask 0x0000000ff0000000 type 6
MTRR: 2 base 0x00000000f0000000 mask 0x0000000fff800000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x00 done.
CPU #0 initialized
PCI: 00:00.0 init ...
Northbridge Init
PCI: 00:04.0 init ...
RTC Init
PCI: 00:04.1 init ...
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: on
IDE: Primary IDE interface, drive 0: UDMA/33: off
IDE: Primary IDE interface, drive 1: UDMA/33: off
IDE: Secondary IDE interface, drive 0: UDMA/33: off
IDE: Secondary IDE interface, drive 1: UDMA/33: off
PCI: 00:04.2 init ...
PCI: 00:06.0 init ...
PCI: 00:07.0 init ...
PCI: 00:09.0 init ...
CBFS: 'Master Header Locator' located CBFS at [100:3ffc0)
CBFS: Locating 'pci102b,0519.rom'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 448c
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 4580
CBFS: File @ offset 4580 size 15800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 4580
CBFS: Checking offset 19e00
CBFS: File @ offset 19e00 size 95eb
CBFS:  Unmatched 'fallback/ramstage' at 19e00
CBFS: Checking offset 23440
CBFS: File @ offset 23440 size 123
CBFS:  Unmatched 'config' at 23440
CBFS: Checking offset 235c0
CBFS: File @ offset 235c0 size 246
CBFS:  Unmatched 'revision' at 235c0
CBFS: Checking offset 23840
CBFS: File @ offset 23840 size f9a9
CBFS:  Unmatched 'fallback/payload' at 23840
CBFS: Checking offset 33240
CBFS: File @ offset 33240 size 61b
CBFS:  Unmatched 'payload_config' at 33240
CBFS: Checking offset 338c0
CBFS: File @ offset 338c0 size ea
CBFS:  Unmatched 'payload_revision' at 338c0
CBFS: Checking offset 33a00
CBFS: File @ offset 33a00 size c0d8
CBFS:  Unmatched '' at 33a00
CBFS: Checking offset 3fb00
CBFS: File @ offset 3fb00 size 3c0
CBFS: 'pci102b,0519.rom' not found.
Option ROM address for PCI: 00:09.0 = f0a20000
PCI expansion ROM, signature 0xaa55, INIT size 0x8000, data ptr 0x0060
PCI ROM image, vendor ID 102b, device ID 0519,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from f0a20000 to 0xc0000, 0x8000 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
0xb102: return 0x48
int1a call returned error.
... Option ROM returned.
VGA Option ROM was run
PCI: 00:0a.0 init ...
PNP: 03f0.0 init ...
PNP: 03f0.1 init ...
PNP: 03f0.2 init ...
PNP: 03f0.3 init ...
PNP: 03f0.5 init ...
PNP: 03f0.7 init ...
PNP: 03f0.a init ...
PNP: 03f0.6 init ...
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:07.0: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PNP: 03f0.6: enabled 1
Finalize devices...
Devices finalized
Copying Interrupt Routing Table to 0x000f0000... done.
Copying Interrupt Routing Table to 0x2fff5000... done.
PIRQ table: 160 bytes.
smbios_write_tables: 2fff4000
Root Device (ASUS P2B-LS)
CPU_CLUSTER: 0 (Intel 82443BX (440BX) Northbridge)
APIC: 00 (Slot 1 CPU)
DOMAIN: 0000 (Intel 82443BX (440BX) Northbridge)
PCI: 00:00.0 (Intel 82443BX (440BX) Northbridge)
PCI: 00:01.0 (Intel 82443BX (440BX) Northbridge)
PCI: 00:04.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PNP: 03f0.0 (Winbond W83977TF Super I/O)
PNP: 03f0.1 (Winbond W83977TF Super I/O)
PNP: 03f0.2 (Winbond W83977TF Super I/O)
PNP: 03f0.3 (Winbond W83977TF Super I/O)
PNP: 03f0.5 (Winbond W83977TF Super I/O)
PNP: 03f0.7 (Winbond W83977TF Super I/O)
PNP: 03f0.8 (Winbond W83977TF Super I/O)
PNP: 03f0.a (Winbond W83977TF Super I/O)
PCI: 00:04.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:04.2 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:04.3 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:06.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:07.0 (unknown)
PCI: 00:09.0 (unknown)
PCI: 00:0a.0 (unknown)
PNP: 03f0.6 (unknown)
SMBIOS tables: 344 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6fdf
Writing coreboot table at 0x2fff6000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000002fff3fff: RAM
 3. 000000002fff4000-000000002fffffff: CONFIGURATION TABLES
 4. 00000000ff800000-00000000ffffffff: RESERVED
CBFS: 'Master Header Locator' located CBFS at [100:3ffc0)
FMAP: Found "FLASH" version 1.1 at 0.
FMAP: base = fffc0000 size = 40000 #areas = 3
Wrote coreboot table at: 2fff6000, 0x1d4 bytes, checksum d81d
coreboot table: 492 bytes.
IMD ROOT    0. 2ffff000 00001000
IMD SMALL   1. 2fffe000 00001000
COREBOOT    2. 2fff6000 00008000
IRQ TABLE   3. 2fff5000 00001000
SMBIOS      4. 2fff4000 00000800
IMD small region:
  IMD ROOT    0. 2fffec00 00000400
  CAR GLOBALS 1. 2fffeac0 00000140
  GDT         2. 2fffe8c0 00000200
CBFS: 'Master Header Locator' located CBFS at [100:3ffc0)
CBFS: Locating 'fallback/payload'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 448c
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 4580
CBFS: File @ offset 4580 size 15800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 4580
CBFS: Checking offset 19e00
CBFS: File @ offset 19e00 size 95eb
CBFS:  Unmatched 'fallback/ramstage' at 19e00
CBFS: Checking offset 23440
CBFS: File @ offset 23440 size 123
CBFS:  Unmatched 'config' at 23440
CBFS: Checking offset 235c0
CBFS: File @ offset 235c0 size 246
CBFS:  Unmatched 'revision' at 235c0
CBFS: Checking offset 23840
CBFS: File @ offset 23840 size f9a9
CBFS: Found @ offset 23840 size f9a9
Loading segment from ROM address 0xfffe3978
  code (compression=1)
  New segment dstaddr 0xe23c0 memsize 0x1dc40 srcaddr 0xfffe39b0 filesize 0xf971
Loading segment from ROM address 0xfffe3994
  Entry Point 0x000ff06e
Bounce Buffer at 2ffbb000, 232048 bytes
Loading Segment: addr: 0x00000000000e23c0 memsz: 0x000000000001dc40 filesz: 0x000000000000f971
lb: [0x0000000000100000, 0x000000000011c538)
Post relocation: addr: 0x00000000000e23c0 memsz: 0x000000000001dc40 filesz: 0x000000000000f971
using LZMA
[ 0x000e23c0, 00100000, 0x00100000) <- fffe39b0
dest 000e23c0, end 00100000, bouncebuffer 2ffbb000
Loaded segments
Jumping to boot code at 000ff06e(2fff6000)
CPU0: stack: 00113000 - 00114000, lowest used address 00113bb0, stack used: 1104 bytes
entry    = 0x000ff06e
lb_start = 0x00100000
lb_size  = 0x0001c538
buffer   = 0x2ffbb000
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
BUILD: gcc: (coreboot toolchain v1.45 June 13th, 2017) 6.3.0 binutils: (GNU Binutils) 2.28
Found mainboard ASUS P2B-LS
Relocating init from 0x000e3940 to 0x2ffa7d80 (size 49632)
Found CBFS header at 0xfffc0138
multiboot: eax=0, ebx=0
Found 10 PCI devices (max PCI bus is 01)
Copying SMBIOS entry point from 0x2fff4000 to 0x000f7140
Copying PIR from 0x2fff5000 to 0x000f70a0
CPU Mhz=1403
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
UHCI init on dev 00:04.2 (io=1800)
ATA controller 1 at 1f0/3f4/0 (irq 14 dev 21)
ATA controller 2 at 170/374/0 (irq 15 dev 21)
Found 1 lpt ports
Found 2 serial ports
ata0-0: Maxtor 6E040L0 ATA-7 Hard-Disk (39205 MiBytes)
Searching bootorder for: /pci at i0cf8/*@4,1/drive at 0/disk at 0
Got ps2 nak (status=51)
DVD/CD [ata1-1: HL-DT-ST DVDRAM GSA-4167B ATAPI-5 DVD/CD]
Searching bootorder for: /pci at i0cf8/*@4,1/drive at 1/disk at 1
All threads complete.
Scan for option roms

Press ESC for boot menu.

Searching bootorder for: HALT
drive 0x000f7030: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=80293248
Space available for UMB: c8000-ee800, f6960-f6fd0
Returned 262144 bytes of ZoneHigh
e820 map has 6 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000002fff4000 = 1 RAM
  4: 000000002fff4000 - 0000000030000000 = 2 RESERVED
  5: 00000000ff800000 - 0000000100000000 = 2 RESERVED
enter handle_19:
  NULL
Booting from DVD/CD...
Device reports MEDIUM NOT PRESENT
scsi_is_ready returned -1
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00

CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.7 | VT102 | Offline | ttyUSB0                                                                                                                                    