[coreboot] New Defects reported by Coverity Scan for coreboot

[scan-admin at coverity.com]

Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

1 new defect(s) introduced to coreboot found with Coverity Scan.


New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)


** CID 1380036:  Control flow issues  (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()


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*** CID 1380036:  Control flow issues  (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
74     	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
75     	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
76     	m_cfg->SaGv = config->SaGv;
77     	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
78     	m_cfg->RMT = config->RMT;
79     
>>>     CID 1380036:  Control flow issues  (NO_EFFECT)
>>>     "i" is converted to an unsigned type because it's compared to an unsigned constant.
80     	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81     		if (config->PcieRpEnable[i])
82     			mask |= (1 << i);
83     	}
84     	m_cfg->PcieRpEnableMask = mask;
85     }


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